Saturation Logic for Mixed-Width Addition Overflow Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
When adding inputs of different widths in hardware arithmetic, integer overflow can occur, leading to inefficiencies and increased hardware area due to the need for long critical paths and additional gates to handle overflow conditions.
Innovation Solution
A method and apparatus for performing addition of inputs, which reduces the area of the hardware and the critical path by determining the risk of integer overflow in parallel and using the carry value and most significant bits to set the output value, thereby reducing the need for interim values wider than the widest input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional addition logic is used to handle inputs of different widths, then the addition can be performed, but integer overflow occurs leading to increased hardware area and longer critical paths
Solution Approach 1:
The patent segments the second input into three distinct parts: the first number of least significant bits, the third number of most significant bits, and a middle section. This segmentation allows parallel processing of overflow detection and addition operations, reducing the critical path length while maintaining accurate overflow detection. The segmented approach enables the circuit to determine overflow risk without requiring the entire addition to complete first, thus improving productivity without proportionally increasing hardware area.
Solution Approach 2:
The patent performs preliminary overflow risk determination by analyzing the most significant bits of the second input before the complete addition is finalized. The carry value from the addition of the first input and the least significant bits of the second input is used in conjunction with the most significant bits to determine overflow risk in advance. This preliminary action allows the circuit to prepare overflow handling logic earlier, reducing the overall critical path length and improving addition speed without requiring excessive hardware resources.
2Reliability
If additional gates are added to handle overflow conditions, then overflow can be detected, but the critical path length increases
Solution Approach 1:
The patent divides the overflow detection process into segments that operate in parallel with the addition process. The most significant bits are analyzed separately from the least significant bits, and the carry value is combined with these bits to determine overflow risk. This segmented detection approach maintains high reliability in overflow detection while avoiding the need for a single long sequential critical path, as different segments can be evaluated concurrently.
Solution Approach 2:
The patent performs preliminary analysis of the most significant bits to determine overflow risk before the complete addition result is available. By using the carry value from the lower bits and combining it with the most significant bits in advance, the circuit can determine overflow conditions earlier in the processing pipeline. This preliminary action reduces the critical path length by eliminating the need to wait for the entire addition to complete before checking for overflow, while maintaining accurate detection through the combination of carry value and most significant bits analysis.
3Reliability
If interim values wider than the widest input are used, then overflow can be accommodated, but hardware area increases
Solution Approach 1:
The patent applies partial action by determining overflow risk based on only the most significant bits and the carry value, rather than requiring the complete addition result. This partial determination approach provides sufficient overflow handling capability without needing to accommodate the full range of possible intermediate values. The circuit achieves reliable overflow detection by focusing on the critical most significant bits and carry information, avoiding the hardware area overhead of supporting wider interim values while maintaining adequate overflow handling capability.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A first input, comprising a first number of bits, and a second input, comprising a second number of bits greater than the first number, are received and added together to determine a carry value. A risk of integer overflow is determined using a third number, equal to the first number subtracted from the second number, of MSBs of the second input. Using the determined carry value and the determined risk of overflow, it is determined whether the addition of the first input and the second input causes integer overflow. In response to determining that the addition causes integer overflow, an output value comprising the second number of bits is determined. The third number of MSBs of the second input is used as the third number of MSBs of the output value. The first number of LSBs of the output value are saturated using the determined risk of integer overflow.