SAW Wafer Package OSP Terminals for Larger IDT Hollow Area
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Solution Overview
Problem
Existing SAW wafer level packages face limitations in increasing the size or number of interdigital transducers due to the vertical passage of connection terminals through the sidewall and cover, requiring complex processes with high-priced equipment and lengthy lead times for forming tin-plating layers.
Innovation Solution
The SAW wafer level package incorporates an organic solderability preservative (OSP) coating layer on the connection terminal, formed through simple processes like dipping, spraying, or spin-coating, which allows for a larger hollow area for IDTs and eliminates the need for high-priced equipment and time-consuming thickness measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection terminals are formed to vertically pass through sidewall and cover, then solderability is improved, but hollow area for IDT is limited
Solution Approach 1:
The connection terminal is reconfigured from a vertical passage through sidewall and cover to a horizontal arrangement on the cover surface. This dimensional change allows the terminal to extend beyond the sidewall periphery rather than penetrating through it, thereby expanding the available hollow area for IDT placement while maintaining solderability through the terminal's exposed surface.
2Reliability
If tin-plating layer is formed through photoresist and electroplating, then solderability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The complex photoresist and electroplating processes are extracted and replaced with a simpler organic solderability preservative (OSP) coating process. The OSP coating can be applied through straightforward methods such as dipping, spraying, or spin-coating, eliminating the need for expensive electroplating equipment and multiple processing steps while still providing adequate solderability for the connection terminal.
3Manufacturing precision
If tin-plating layer thickness is measured for quality control, then manufacturing precision is improved, but lead time increases
Solution Approach 1:
The patent accepts a thinner, less durable tin-plating layer (1-3 μm) compared to traditional requirements, trading off some long-term durability for significantly reduced manufacturing time. The OSP coating provides sufficient solderability without requiring thick plating or extensive quality control measurements, thereby reducing lead time while maintaining functional adequacy for the application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables increased IDT size or number, reduces manufacturing time and costs by simplifying the process, and improves solderability without the need for complex photoresist and electroplating steps.
Implementation Method 1
formed through simple processes like dipping, spraying, or spin-coating
Data Source
AI summary
A surface acoustic wave wafer level package includes a substrate, an interdigital transducer (IDT) formed on the substrate, a sidewall formed on the substrate along a periphery of the IDT, a cover formed above the sidewall and the IDT to form a hollow above the IDT with the sidewall, a connection electrode formed on the substrate and extending outward from a periphery of the sidewall, a connection terminal electrically connected to a part of the connection electrode which extends outward from the periphery of the sidewall, and an organic solderability preservative coating layer formed on at least a top surface of the connection terminal.