SAW Package Structure With Pillar Bump for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional SAW devices face challenges with increased parasitic capacitance and reduced performance due to larger package sizes and insufficient heat dissipation, especially when trying to accommodate more IDT finger pairs for improved frequency response.
Innovation Solution
The SAW device design incorporates a piezoelectric substrate, a supportive layer, a cover layer, and a pillar bump structure that reduces parasitic capacitance by minimizing the difference between the transducer receiving space and the package area, while also enhancing heat dissipation through the protruded pillar bump.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the package size is increased to accommodate more IDT finger pairs for improved frequency response, then the frequency response capability is improved, but the parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The patent embeds the transducer directly within the package structure by forming the supportive layer around the transducer and creating via holes that pass through both the supportive layer and cover layer. This nested configuration allows the transducer to be tightly integrated into the package, minimizing the difference between receiving space area and package area, thereby reducing parasitic capacitance while maintaining frequency response capability.
Solution Approach 2:
The patent utilizes the vertical dimension by forming via holes that extend through the thickness of the supportive and cover layers. The pillar bump structure protrudes from the lateral surface of the cover layer, effectively using three-dimensional space rather than expanding the planar package area. This dimensional approach reduces parasitic capacitance while accommodating the transducer.
2Reliability
If the number of IDT finger pairs is increased to improve frequency response, then the frequency response capability is improved, but the device size must be increased which conflicts with miniaturization requirements
Solution Approach 1:
The transducer is nested within the package structure formed by the supportive layer and cover layer. The via holes and pillar bump create a compact three-dimensional arrangement that maximizes the use of available space, allowing more IDT finger pairs to be accommodated within the same package area, thus improving frequency response without increasing device size.
Solution Approach 2:
By utilizing the vertical dimension through via holes and the protruding pillar bump structure, the patent effectively increases the available volume for the transducer without expanding the planar package area. This allows for more IDT finger pairs to be packed into the same footprint, achieving better frequency response while maintaining miniaturization.
3Reliability
If the number of IDT finger pairs is increased to improve frequency response, then the frequency response capability is improved, but the heat generated by IDT increases and the device becomes unstable when heat dissipation is insufficient
Solution Approach 1:
The patent extracts the heat dissipation function by forming a pillar bump that protrudes from the lateral surface of the cover layer. This pillar bump structure provides an extended thermal path that conducts heat away from the transducer more effectively. The via holes also serve as thermal conduction pathways, extracting heat from the transducer region and dissipating it through the package structure, thereby maintaining stability even with increased IDT finger pairs.
4Area of stationary object
If the package area is reduced to meet miniaturization requirements, then the device size is reduced, but the space for receiving transducer is limited which restricts frequency response capability
Solution Approach 1:
The patent compensates for limited planar space by utilizing the vertical dimension. Via holes are formed through the supportive and cover layers, and the pillar bump protrudes laterally, effectively using three-dimensional space. This allows the transducer to be compactly arranged within a small package area while still accommodating sufficient IDT finger pairs for good frequency response capability.
Solution Approach 2:
The transducer is nested within the package structure, with the supportive layer surrounding it and via holes providing both electrical connection and thermal management. This nested configuration maximizes space utilization, allowing the transducer to be tightly integrated into a compact package while maintaining the necessary IDT finger pairs for frequency response capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves reduced parasitic capacitance, improved performance with increased transducer capacity, and enhanced stability due to effective heat dissipation, all while minimizing the package size.
Implementation Method 1
a piezoelectric substrate, a wall, a lid, a bump and a solder cap. The piezoelectric substrate includes a carrier, a pad and an interdigital transducer (IDT)
Implementation Method 2
The pillar bump is disposed in the lower via hole and the upper via hole and connected to the conductive pad. The pillar bump in the cover layer includes a first part and a second part, the first part is located in the upper via hole and the second part is protruded from the lateral surface of the cover layer via the first lateral opening of the upper via hole.
Data Source
AI summary
A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.