Bonded SAW Wafers With Low-Carrier-Lifetime Silicon Interface

Solution Overview

Problem

Surface Acoustic Wave (SAW) filters using bonded wafers with piezoelectric layers on silicon substrates face performance degradation due to parasitic conductance, which limits the quality factor (Q) and prevents the use of thinner piezoelectric layers that could reduce losses and spurious modes.

Innovation Solution

A bonded wafer with a silicon substrate having a modified top portion with reduced carrier lifetime, where the piezoelectric layer is bonded over the silicon substrate with a thickness less than 2 times the wavelength, and optionally an insulation layer is included to prevent parasitic conductance and enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a thinner piezoelectric layer is used, then acoustic losses and spurious modes are reduced, but parasitic conductance increases and quality factor degrades

Engineering Contradiction:

Improveacoustic lossesVSAvoidquality factor

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by creating a non-uniform doping profile in the silicon substrate, specifically forming a low-carrier lifetime region at the top surface that differs from the bulk substrate. This localized modification prevents parasitic conductance formation at the critical interface region while preserving the beneficial effects of a thin piezoelectric layer, thereby resolving the contradiction between reducing acoustic losses and maintaining quality factor.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of carrier lifetime in the silicon substrate by introducing specific doping profiles. By reducing the carrier lifetime parameter in the top portion of the substrate through controlled doping, the patent eliminates parasitic conductance formation, allowing thin piezoelectric layers to operate without quality factor degradation while still suppressing acoustic losses and spurious modes.

Inventive Principle:

Principle #35Parameter changes

2Object-generated harmful factors

If a thinner piezoelectric layer is used, then spurious modes are suppressed, but parasitic conductance prevents quality factor improvement

Engineering Contradiction:

Improvespurious modesVSAvoidquality factor

Core Design Contradiction:

Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent applies local quality by creating a non-uniform doping profile in the silicon substrate, specifically forming a low-carrier lifetime region at the top surface that differs from the bulk substrate. This localized modification prevents parasitic conductance formation at the critical interface region while preserving the beneficial effects of a thin piezoelectric layer, thereby resolving the contradiction between reducing acoustic losses and maintaining quality factor.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of carrier lifetime in the silicon substrate by introducing specific doping profiles. By reducing the carrier lifetime parameter in the top portion of the substrate through controlled doping, the patent eliminates parasitic conductance formation, allowing thin piezoelectric layers to operate without quality factor degradation while still suppressing acoustic losses and spurious modes.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution allows for a thinner piezoelectric layer without degrading the quality factor, reducing parasitic conductance and enhancing the performance of SAW filters by maintaining or improving the quality factor and suppressing spurious modes.

Implementation Method 1

modifying a top portion of the silicon substrate to reduce carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion

Methodology Applied

Scientific EffectCarrier lifetime reduction:

Implementation Method 2

If the acoustic velocity of the support substrate is larger than the acoustic velocity in the piezoelectric film, the acoustic wave is guided inside the film and the losses into the bulk are suppressed

Methodology Applied

Scientific EffectSurface acoustic wave propagation: Surface Acoustic Wave

Implementation Method 3

the acoustic wave is guided inside the film and the losses into the bulk are suppressed

Methodology Applied

Scientific EffectAcoustic wave guidance: Waveguide

Data Source

PatentUS10381998B2Methods for fabrication of bonded wafers and surface acoustic wave devices using same

Publication Date: 2019.08.13 QORVO US INC

AI summary

A method of fabricating a bonded wafer with low carrier lifetime in silicon comprises providing a silicon substrate having opposing top and bottom surfaces, modifying a top portion of the silicon substrate to reduce carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion, bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate, and providing a pair of electrodes having fingers that are inter-digitally dispersed on a top surface of the piezoelectric layer, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. The modifying and bonding steps may be performed in any order. The modified top portion of the silicon substrate prevents the creation of a parasitic conductance within that portion during operation of the SAW device.