Sawtooth Electric Field Drift Region for Power Semiconductors
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Solution Overview
Problem
Conventional semiconductor power devices face limitations in achieving optimal electric field profiles in the drift region, leading to increased thickness and reduced performance in voltage blocking and switching speed due to trade-offs between forward blocking voltage and on-state voltage drop.
Innovation Solution
Implementing rows of multiple horizontal columns of thin layers of alternating P-type and N-type conductivity in the drift region, ensuring charge balance and allowing the P-type layers to undergo punch through, resulting in a sawtooth-shaped electric field profile that reduces drift region thickness by 20% while maintaining high voltage blocking capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reduced doping concentration in the drift region is used to block high voltages, then the voltage blocking capability is improved, but the resistance increases and forward conduction performance deteriorates
Solution Approach 1:
The drift region is segmented into multiple alternating P-type and N-type doped layers, creating a multi-layered structure. This segmentation allows the region to simultaneously achieve high voltage blocking (through the low-doped N-type layers) and low resistance (through the highly doped P-type layers), resolving the contradiction between voltage blocking capability and forward conduction loss
Solution Approach 2:
Different regions of the drift structure are assigned different doping concentrations and types. The N-type layers have low doping for voltage blocking, while the P-type layers have high doping for reducing resistance. This local differentiation of properties allows simultaneous optimization of both voltage blocking and forward conduction characteristics
2Loss of energy
If bipolar devices are used to improve on-state voltage drop through minority carrier injection, then the forward conduction performance is improved, but the switching performance degrades
Solution Approach 1:
The device structure enables dynamic control of carrier injection. During forward conduction, the alternating P-N layers facilitate minority carrier injection to reduce on-state voltage drop. During switching, the structure allows rapid carrier removal. This dynamic behavior enables the device to achieve low on-state voltage drop without significant degradation in switching performance
3Device complexity
If a conventional triangular or trapezoidal electric field profile is used, then the device structure is simple, but the drift region thickness must be greater than necessary
Solution Approach 1:
The drift region is divided into multiple alternating P-type and N-type layers, creating a segmented structure that generates a sawtooth electric field profile. This segmentation enables the electric field to be more uniformly distributed, allowing the drift region thickness to be reduced by approximately 20% compared to conventional triangular or trapezoidal profiles while maintaining the same voltage blocking capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The sawtooth electric field profile achieves optimal voltage blocking with a thinner drift region, reducing resistance and improving switching speed without compromising breakdown voltage, thus enhancing the performance of semiconductor power devices like IGBTs, power MOSFETs, and power diodes.
Implementation Method 1
achieve a sawtooth shaped electric field profile
Implementation Method 2
the P type layers are chosen such that they undergo punch through via the built-in potential from the N layers on their top and bottom
Data Source
AI summary
This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP<2*WD*[ND/(NA+ND)] where ND and WN represent the doping concentration and the thickness of the N type layers 160, while NA and WP represent the doping concentration and thickness of the P type layers; WD represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges. In another exemplary embodiment, the semiconductor power device further includes a sawtooth insulated gate bipolar transistor (IGBT). In another exemplary embodiment, the semiconductor power device further includes a metal oxide semiconductor field effect transistor (MOSFET). In another exemplary embodiment, the semiconductor power device further includes a power diode.