Scalable Packet Reception Ring Architecture for Multi-Core Throughput
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Solution Overview
Problem
Typical systems experience bottlenecks in packet reception and transmission due to a single core processing all packet pointers, limiting scalability and throughput as they struggle to move receive data pointers into an application queue and transmit data from the application queue to a network interface card.
Innovation Solution
Implementing a network device with a shared ring in memory that allocates multiple processor cores to different stages of a processing pipeline, including input, worker, and output stages, allowing for independent filling of receive and transmit descriptors and buffers, reducing bottlenecks by using direct memory access (DMA) and offloading software thread dependencies to hardware components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single core processes all packet pointers from the network interface card, then the system structure remains simple, but the throughput is limited and scalability is prevented when throughput exceeds the capacity of the single core
Solution Approach 1:
The patent divides the packet processing workload into multiple segments by creating separate receive queues for different cores. Each core has its own queue and processes packets independently, transforming the single-threaded bottleneck into a multi-threaded parallel processing system that scales with the number of cores
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing packet processing across multiple cores simultaneously. Instead of sequential processing on one core, the system distributes packet pointer processing across multiple cores in parallel, effectively adding a dimensional layer to the processing architecture
2Productivity
If a single core moves receive data pointers into the application queue, then the control logic remains simple, but the bottleneck prevents scalability when throughput exceeds core capacity
Solution Approach 1:
The patent segments the packet pointer movement operation by assigning different receive queues to different cores. Each core independently moves packet pointers from the network interface card to its dedicated application queue, eliminating the sequential bottleneck and enabling concurrent packet processing across multiple cores
Solution Approach 2:
Each core independently manages its own receive queue and packet processing without requiring coordination or intervention from other cores. This self-service approach eliminates inter-core dependencies and synchronization overhead, allowing each core to process packets at its own pace without creating bottlenecks
3Productivity
If a single core transmits packets from the application queue to the network interface card, then the transmission control remains simple, but the bottleneck limits transmission throughput
Solution Approach 1:
The patent divides the transmission function into multiple independent transmit queues, each associated with a specific core. Each core independently transmits packets from its assigned queue to the network interface card, transforming the single-point transmission bottleneck into a distributed parallel transmission system
Solution Approach 2:
Multiple cores are equipped with identical transmission capabilities, allowing any core to perform packet transmission to the network interface card. This universal transmission capability across all cores enables the system to scale transmission throughput by utilizing any available core for transmission tasks
Data Source
AI summary
Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.