Scaled Gain Cell Layout for Low-Temperature Dense RAM
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Solution Overview
Problem
Current memory devices face challenges in achieving higher density and lower costs, which are essential for improving system performance and reducing complexity and costs in larger systems.
Innovation Solution
The implementation of scaled bit cells with staggered read and write transistors and parallel, offset channel structures in random-access memory (RAM) devices, allowing for shared contacts and compact layouts, reduced component sizes, and lower system temperatures, thereby enhancing memory density and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device density is increased to improve system performance, then memory capacity improves, but manufacturing complexity and cost reduction become more difficult
Solution Approach 1:
The bit cell is segmented into distinct functional regions with staggered transistor placements. The read transistor and write transistor are positioned at different locations within the bit cell, allowing independent optimization of each transistor's characteristics and simplifying the manufacturing process for high-density arrays.
Solution Approach 2:
The patent transitions from planar transistor layouts to vertically stacked channel structures. Multiple channel structures are stacked in the vertical dimension, enabling higher memory density without proportionally increasing lateral manufacturing complexity.
2Quantity of substance
If component sizes are reduced to increase memory density, then memory capacity improves, but leakage currents increase
Solution Approach 1:
Different regions of the bit cell are given different properties to optimize performance. The read transistor and write transistor have different channel structures and materials tailored to their specific functions, allowing small component sizes while controlling leakage through localized material optimization.
Solution Approach 2:
The patent uses composite channel structures with different materials in different regions. High-mobility materials are used where needed for performance, while materials with better leakage characteristics are used in other regions, achieving low leakage in scaled components.
3Use of energy by moving object
If operating temperature is reduced to lower voltage requirements, then power consumption improves, but manufacturing and operation complexity increase
Solution Approach 1:
The patent changes the physical parameters of the channel structures, including material composition and dimensional characteristics, to optimize performance at reduced operating temperatures. This allows lower voltage operation while managing the complexity of temperature control through material selection rather than complex active cooling systems.
Data Source
AI summary
Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.