Scan Chain Control Elements for Laser IC Testing
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Solution Overview
Problem
Laser-based testing of integrated circuits faces challenges due to signal crosstalk and coupling from adjacent signals, which cause distortion and affect the accuracy of fault isolation techniques like LVI and LVP, especially as feature sizes decrease and signal density increases, leading to increased testing time and potential IC damage from high-frequency shifting.
Innovation Solution
The implementation of scan chain control elements that selectively enable or disable test data flow to specific scan chains, allowing for focused laser-based testing by quieting unselected scan chains and using larger laser probe cells to reduce cross-talk and coupling, thereby improving testing accuracy and reducing power consumption and heat production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the spot size of the laser is reduced to improve optical resolution and mapping accuracy, then measurement precision is improved, but signal crosstalk and coupling from adjacent signals increases due to higher signal density in smaller feature sizes
Solution Approach 1:
The patent introduces scan chain control elements as intermediary components between the laser probing system and the scan chains. These control elements selectively enable or disable specific scan chains during testing, acting as a mediator that isolates the target scan chain from adjacent signals. This prevents signal crosstalk and coupling while maintaining the ability to use smaller laser spot sizes for improved optical resolution and measurement accuracy.
2Productivity
If high-frequency shifting is used to reduce testing time, then productivity is improved, but the risk of IC damage increases
Solution Approach 1:
The patent divides the scan testing process into segments by introducing scan chain control elements that allow selective activation of individual scan chains. This segmentation enables controlled, staggered testing of different scan chains at different times, reducing the overall frequency and intensity of simultaneous switching activity. Consequently, testing productivity is maintained through efficient scan chain utilization while the risk of IC damage from high-frequency shifting is mitigated.
3Productivity
If multiple scan chains are tested simultaneously to improve productivity, then productivity is improved, but signal distortion increases due to increased crosstalk and coupling
Solution Approach 1:
The patent implements dynamic control of scan chain testing through scan chain control elements that can selectively enable or disable specific scan chains based on testing requirements. This dynamic approach allows the system to adaptively manage the number of active scan chains during different phases of testing. When signal accuracy is critical, fewer scan chains are activated simultaneously, reducing crosstalk. When productivity is the priority, more scan chains can be tested with appropriate control, optimizing the balance between throughput and signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of laser-based fault isolation and reduces testing time and power consumption, enabling effective diagnosis of IC failures even at smaller feature sizes, such as 10 nm and beyond, while minimizing the risk of IC damage from high-frequency shifting.
Implementation Method 1
LVP, on the other hand, enables timing measurement of internal signals within an IC, when transistors are switching. Thus, LVP enables non-contact probing of signals
Implementation Method 2
A typical solid immersion lens (SIL) of an LVI or LVP system would have a spot size of ~300 nm
Data Source
AI summary
The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.