Scan Chain Hold Time Fault Localization Under Variable Test Conditions
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Solution Overview
Problem
As technology nodes shrink, scan chains in integrated circuits increasingly suffer from defects such as hold time faults, which disrupt data communication and mask other failures, leading to yield loss and inaccurate testing.
Innovation Solution
The methods involve determining and analyzing hold time faults in scan chains by varying environmental variables like supply voltage and temperature, using non-constant sequence patterns and background patterns to identify and locate faults, allowing for precise determination of fault numbers and locations within the scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If scan chains are used for testing integrated circuits, then test coverage is improved, but hold time faults and other defects increase due to technology node shrinkage
Solution Approach 1:
The patent applies preliminary action by performing chain integrity tests and hold time fault analysis before actual device testing. The system pre-identifies and characterizes scan chain defects using specific test patterns (like 00110011 sequences) and environmental variable variations, so that when real testing occurs, the scan chains are already known to be functional or problematic, preventing false test results.
Solution Approach 2:
The patent utilizes parameter changes by varying environmental variables (temperature, supply voltage) during scan chain testing. By testing at multiple temperature points and voltage levels, the system can detect hold time faults that only manifest under specific conditions, thereby improving scan chain reliability assessment without compromising test coverage.
2Ease of operation
If conventional testing methods are used, then testing is simpler, but hold time faults mask other failures leading to inaccurate testing
Solution Approach 1:
The patent applies segmentation by dividing the testing process into distinct phases: chain integrity testing, hold time fault analysis, and actual device testing. It also segments the test patterns into specific sequences (00110011, 01010101, etc.) that target different fault types. This segmentation allows the system to maintain operational simplicity while achieving high testing accuracy by isolating and addressing hold time faults separately.
Solution Approach 2:
The patent introduces an intermediary analysis step between conventional testing and actual device testing. The hold time fault analysis module acts as an intermediary that processes scan chain outputs and determines whether hold time faults are present before allowing main testing to proceed. This intermediary layer prevents masked failures from compromising overall test accuracy.
3Reliability
If scan chains are added for testing purposes, then defect detection capability is improved, but yield loss increases due to blocked chains and other defects
Solution Approach 1:
The patent applies preliminary action by performing comprehensive scan chain characterization and integrity testing before production testing. By pre-identifying blocked chains, hold time faults, and other scan chain defects, the system can separate good devices from bad ones earlier in the process, preventing good devices from being mistakenly rejected due to scan chain failures, thereby reducing yield loss while maintaining defect detection capability.
Solution Approach 2:
The patent utilizes parameter changes by testing scan chains under varying environmental conditions (temperature, voltage) to distinguish between scan chain defects and actual device failures. By observing how scan chain behavior changes with environmental parameters, the system can more accurately attribute failures to their true causes, reducing false positives and improving yield without compromising defect detection.
Data Source
AI summary
In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.