Semiconductor Integrated Circuit Scan Chain Loop Operation

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Solution Overview

Problem

Existing semiconductor integrated circuits face challenges in efficiently managing power consumption during scan testing, leading to potential errors and instability due to rapid power increases and voltage drops, which can affect fault detection accuracy.

Innovation Solution

The implementation of a semiconductor integrated circuit with multiple scan chains operating on different clock signals, allowing for a loop operation before the scan shift operation to differentiate the timing of flip-flop start-ups and form closed loops, thereby reducing power consumption spikes and maintaining data stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If scan testing is performed with multiple scan chains operating simultaneously, then testing efficiency is improved, but power consumption increases rapidly causing voltage drops and reducing reliability

Engineering Contradiction:
Improvetesting efficiencyVSAvoidfault detection accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the scan testing process into two distinct phases: a loop operation phase where scan chains form closed loops and circulate data, and a scan shift operation phase where actual fault detection occurs. This segmentation allows the system to maintain high testing efficiency while managing power consumption by separating the high-speed data circulation function from the power-intensive fault detection function.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The loop operation is performed as a preliminary action before the scan shift operation. During this preliminary phase, test data is circulated through closed loops formed by multiplexers connecting scan chain outputs back to inputs, preparing the system for fault detection without requiring full power consumption. This preliminary data circulation establishes stable test conditions before the actual fault detection begins.

Inventive Principle:
Principle #10Preliminary action

2Speed

If multiple scan chains operate simultaneously during scan testing, then testing speed is improved, but voltage drops occur due to power consumption spikes

Engineering Contradiction:
Improvetesting speedVSAvoidvoltage stability
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent implements periodic action by alternating between loop operation cycles and scan shift operation cycles. During loop operation cycles, scan chains circulate test data in closed loops at high speed. During scan shift operation cycles, the system performs fault detection. This periodic alternation allows the power consumption to be distributed over time, preventing sustained high power consumption that would cause voltage drops, while maintaining high testing speed through the efficient loop operation phase.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If scan chains use different clock signals for operation, then flexibility in timing control is improved, but system complexity increases

Engineering Contradiction:
Improvetiming control flexibilityVSAvoidclock signal management
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent makes the multiplexer component universal by enabling it to perform multiple functions: during the loop operation phase, multiplexers connect scan chain outputs back to their respective inputs to form closed loops; during the scan shift operation phase, the same multiplexers redirect data flow to enable fault detection. This multi-functionality allows different clock signals to be used for different phases without requiring separate control circuits for each mode, thereby maintaining timing control flexibility while limiting the increase in system complexity to the inherent multiplexer structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20210286926A1Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method
Publication Date: 2021.09.16 KK TOSHIBA
  • US20210286926A1 patent drawing
  • US20210286926A1 patent drawing
  • US20210286926A1 patent drawing

AI summary

According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.