Scan-Chain PUF Generation for Clone-Resistant Chip Authentication
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Solution Overview
Problem
Physically unclonable functions (PUFs) in semiconductor devices face limitations in providing robust security due to their vulnerability to tampering and hacking, as they rely on uncontrolled manufacturing variations for their uniqueness, which can be challenging to maintain and protect.
Innovation Solution
A method is introduced that generates a second physically unclonable function based on a first PUF by shifting power-up values through scan chain logic and combinatorial logic, using challenge words to create a strong PUF that is resistant to unauthorized access and cloning, by leveraging the unique physical and electrical characteristics of the chip during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PUFs are used for device identification, then device uniqueness is achieved through manufacturing variations, but security robustness deteriorates due to vulnerability to tampering and hacking
Solution Approach 1:
The PUF circuit is divided into multiple independent flip-flops arranged in scan chains, where each flip-flop contributes to the overall unique response. This segmentation allows the system to maintain security robustness while achieving device uniqueness, as the distributed structure resists tampering better than centralized PUF implementations.
Solution Approach 2:
The patent implements a hierarchical PUF structure where multiple levels of uniqueness are nested within each other. The first level uses manufacturing variations in individual flip-flops, while the second level uses the arrangement and configuration of scan chains. This nested approach enhances security robustness by creating multiple layers of protection against tampering and hacking.
2Reliability
If scan chain logic is enabled for generating PUF responses, then security resistance to cloning is improved, but device complexity increases due to additional logic circuits
Solution Approach 1:
The scan chain logic is designed to serve multiple functions: it enables PUF response generation for security authentication while also supporting standard testing and debugging operations. This multi-functionality reduces the need for separate dedicated security circuits, thereby limiting the increase in device complexity while maintaining strong cloning resistance.
Solution Approach 2:
The PUF generation mechanism utilizes the existing scan chain infrastructure that is already present in most semiconductor devices for testing purposes. By making the scan chains serve the additional function of PUF response generation, the system achieves strong security resistance to cloning without requiring completely new dedicated hardware, thus limiting complexity increase.
Data Source
AI summary
A method for controlling access to a chip includes obtaining first values of a first physically unclonable function of the chip, obtaining second values that correspond to at least one challenge word, performing a simulation based on the first values and the second values, and generating an authentication result for the chip based on results of the simulation. The simulation may generate responses to logical operations corresponding to combinatorial logic in the chip, and the logical operations may be performed based on a predetermined sequence of the first values and the second values. The chip may be authenticated based on a match between the responses generated by the simulation and a second physically unclonable function of the chip.