Dynamic Scan Chain Power Control via Toggle Monitoring
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Solution Overview
Problem
Existing scan chain testing methods face challenges in managing power consumption during testing, as they often require conservative static schedules that reduce scan data bandwidth and increase testing time, especially in complex system-on-chip (SoC) circuits with multiple modules, and additional circuitry can introduce timing delays and area overhead.
Innovation Solution
A method that determines toggling events in a test sequence and selectively times the input of bit sequences to storage elements in the scan chain, using a toggle limit and dynamic clock delay to manage power consumption by temporarily suspending clocking when the toggle limit is exceeded, thereby reducing power load without compromising testing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If static schedules are used to limit test power consumption by selectively enabling/disabling scan chains, then power consumption is controlled, but scan data bandwidth is reduced and testing time increases
Solution Approach 1:
The patent applies dynamic control by monitoring toggle activity in real-time during scan testing and dynamically adjusting the enabling/disabling of scan chains based on current power consumption levels. This replaces static schedules with a dynamic system that can respond to actual operating conditions, allowing scan chains to be enabled when power headroom exists and disabled when power limits are approached, thereby maintaining both power control and optimal testing speed
Solution Approach 2:
The patent implements feedback control by continuously monitoring toggle activity metrics during scan testing and using this information to adjust scan chain configuration. The system measures actual power consumption indicators (toggle counts) and feeds this information back to control logic that determines which scan chains should be active, creating a closed-loop system that adapts to real-time conditions rather than following predetermined static schedules
2Use of energy by stationary object
If additional gating circuitry is added to block flip flop outputs during scan testing, then power consumption is reduced, but area is increased and timing delays are introduced
Solution Approach 1:
The patent makes existing control structures multi-functional by having the scan chain enable/disable logic serve dual purposes: controlling power consumption during testing and managing test data flow. Instead of adding separate gating circuitry, the system uses the same control mechanisms that manage scan chain activation to also control power, thereby achieving power reduction without increasing circuit area or introducing additional timing delays
3Use of energy by stationary object
If conservative static schedules are imposed on scan shift operation, then power consumption is limited, but the time required to test the DUT increases
Solution Approach 1:
The patent transitions from conservative static schedules to dynamic power management that adjusts scan chain activation in real-time based on measured toggle activity. This allows the system to operate at higher speeds when power conditions permit while still enforcing power limits when necessary, thereby reducing total testing time compared to static approaches that must always operate conservatively
Solution Approach 2:
The patent changes the operational parameters of scan testing by using toggle activity metrics as a basis for dynamic adjustment of scan chain configuration. Instead of fixed parameters determined before testing, the system continuously adapts parameters (which scan chains are active, at what speed) based on real-time measurements, allowing optimization of both power consumption and testing speed throughout the test process
Data Source
AI summary
A method of testing a device under test, the device under test comprising a scan chain having a number of storage elements. The method determines a representation of toggling events in a test sequence, where the test sequence is for testing the scan chain. The method also selectively times input of a bit sequence, corresponding to the test sequence, to a first storage element in the number of storage elements, and through the scan chain, in response to the determining step.