Scan Circuit Layout for Stable Display Gate Driving Signals
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Solution Overview
Problem
Existing scan circuits in display technology suffer from fluctuations in output signals, leading to jittering of gate driving signals that adversely affect display quality.
Innovation Solution
The scan circuit incorporates intricate layout structures for capacitors and transistors, including a first capacitor and sixth transistor with overlapping connections, and optimized transistor configurations to reduce coupling fluctuations between clock signals, thereby stabilizing gate driving signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan circuit layouts are used, then device complexity is reduced, but signal fluctuations increase leading to jittering gate driving signals
Solution Approach 1:
The scan circuit is divided into multiple stages, with each stage containing specific transistor and capacitor configurations. This segmentation allows independent optimization of each stage to reduce signal fluctuations while maintaining overall circuit functionality.
Solution Approach 2:
Specific layouts are designed for capacitors and transistors in particular stages, with optimized transistor configurations and connections tailored to reduce coupling fluctuations and parasitic capacitance in critical signal paths.
2Reliability
If standard transistor configurations are used, then manufacturing is simplified, but coupling fluctuations and parasitic capacitance increase
Solution Approach 1:
The patent optimizes transistor configuration parameters such as channel width-to-length ratios and connection topologies to minimize coupling fluctuations and parasitic capacitance effects, thereby improving signal stability.
3Reliability
If simple connecting line layouts are used, then device complexity is reduced, but signal interference and fluctuations increase
Solution Approach 1:
The connecting lines are routed through multiple layers and dimensions to cross over capacitor electrodes and other signal paths, reducing parasitic capacitance and signal interference by utilizing three-dimensional space rather than planar layouts.
Data Source
AI summary
A scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a second processing subcircuit, which includes a first capacitor, a sixth transistor, and a seventh transistor; and a first connecting line connecting a gate electrode of the seventh transistor to a second clock signal line; and a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together. The sixth connecting line crosses over both a first capacitor electrode and the second capacitor electrode of the first capacitor. An orthographic projection of the first connecting line on a base substrate at least partially overlaps with an orthographic projection of the sixth connecting line on the base substrate.