Scan Clock Partitioning for IR Drop Reduction in SoC Testing
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Solution Overview
Problem
In synchronous circuits, particularly in System on Chip (SoC) devices, the simultaneous clocking of hundreds of thousands of flip-flops during scan testing leads to instantaneous voltage drops (IR Drop) across clock lines, causing timing violations and potential failures due to excessive power consumption, which complicates testing and reduces yield.
Innovation Solution
The solution involves partitioning large synchronous clock domains into multiple partitions, allowing staggered or phase-shifted clock signals during the shift operation to distribute switching activity, thereby reducing IR Drop and enabling reliable testing in a single pass without design complexity increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all flip flops are clocked simultaneously during scan shift operation, then testing completeness is improved, but instantaneous voltage drop increases causing timing violations
Solution Approach 1:
The patent divides the large synchronous circuit into multiple scan partitions, each with its own scan chain. During scan shift operations, not all partitions are clocked simultaneously - only a subset is activated at each time step. This segmentation allows the testing of all flip flops to be distributed across multiple time steps, reducing the instantaneous current draw and voltage drop while still achieving complete testing coverage.
2Object-affected harmful factors
If scan partitions are used to reduce IR drop, then voltage stability is improved, but test time increases due to serialized testing
Solution Approach 1:
The patent employs dynamic scan partitioning where the set of active scan partitions changes over time. Different combinations of scan partitions are activated in different time steps, allowing the system to adaptively balance between reducing instantaneous current draw and maintaining reasonable test throughput. This dynamic approach prevents any single partition from being over-tested while ensuring all partitions are eventually tested.
Solution Approach 2:
The patent implements periodic activation of scan partitions in a rotating manner. Each scan partition is activated for a certain number of time steps, then deactivated while another partition becomes active. This periodic rotation ensures that all partitions are tested over the course of the test sequence, but never simultaneously, thereby controlling the instantaneous power consumption and voltage drop while maintaining complete test coverage.
3Device complexity
If a single clock domain is used for all logic, then device complexity is reduced, but switching activity during shift operation increases causing power issues
Solution Approach 1:
The patent segments the monolithic clock domain into multiple smaller scan partition clock domains. Each scan partition has its own clock signal that can be independently controlled. This segmentation maintains relative simplicity compared to fully independent clock domains for each logic block, while enabling selective activation of partitions during scan operations to reduce overall switching activity and power consumption.
Data Source
AI summary
An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.