Scan Data Control Apparatus for SoC Hardware Malfunction Analysis
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Solution Overview
Problem
As the integration degree of System on Chip (SoC) increases, analyzing hardware malfunctions becomes more difficult due to the complexity of integrating various semiconductor components, and software logs alone are insufficient to determine the cause of malfunctions, especially when they stem from hardware issues.
Innovation Solution
A scan data control apparatus is introduced, comprising a trigger part, scan sequencer, shift register, and transmitter, which detects system malfunctions and stores scan data from the CPU and master within a memory, enabling analysis of hardware logic by transitioning them into a scan mode and storing the data for later analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration degree of SOC increases, then the operational speed and component density improve, but the difficulty of analyzing hardware malfunctions increases
Solution Approach 1:
The patent implements preliminary action by capturing and storing scan data in memory before a malfunction occurs or at the moment of malfunction. The scan data control apparatus continuously monitors and stores hardware state information, enabling post-event analysis without requiring complex real-time debugging tools. This preliminary data collection resolves the contradiction by preparing diagnostic information in advance, making malfunction analysis feasible despite high integration complexity.
Solution Approach 2:
The patent applies copying by creating a duplicate representation of the hardware state through scan data stored in memory. Instead of directly analyzing the complex physical hardware circuitry, the system captures a copy of the signal waveforms and state information, which can then be analyzed externally using standard equipment. This copying approach simplifies the analysis process while maintaining full diagnostic capability.
2Ease of manufacture
If software logs are used for debugging, then the implementation is simple, but the ability to determine hardware malfunction causes is insufficient
Solution Approach 1:
The patent merges software logging simplicity with hardware diagnostic precision by combining scan data capture from hardware circuits with memory storage and external analysis capability. The system integrates the scan data control apparatus that interfaces with both the hardware circuitry under test and the memory system, creating a unified debugging solution that retains the ease of software implementation while gaining hardware-level diagnostic precision.
Solution Approach 2:
The patent introduces an intermediary element - the scan data control apparatus and memory system - that bridges software debugging simplicity and hardware diagnostic precision. This intermediary captures hardware state information, stores it in memory, and makes it accessible for analysis, thereby translating complex hardware states into analyzable data formats without requiring direct complex hardware interaction.
3Measurement precision
If additional debugging tools are used to analyze hardware malfunctions, then the diagnostic precision improves, but the system complexity and cost increase
Solution Approach 1:
The patent implements self-service by enabling the system to debug itself using its own existing resources. The scan data control apparatus utilizes the system's own memory and existing scan chain infrastructure to capture and store diagnostic data. This self-service approach achieves high diagnostic precision without requiring external specialized debugging equipment, thereby avoiding increased system complexity and cost.
Data Source
AI summary
A scan data control apparatus includes a trigger circuit, a scan sequencer, a shift register, and a transmitter. The trigger circuit is configured to receive a trigger signal, detect a malfunction of a system and output a scan mode start signal and a scan mode end signal. The scan sequencer is configured to output scan enable signals corresponding to a CPU and a master to the CPU and the master. The shift register is configured to receive scan data of the CPU and the master from the CPU and the master. The transmitter is configured to receive the scan data of the CPU and the master and output the scan data to a memory.