Scan Driver Pulse Width Control for Uniform Display Charging

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Solution Overview

Problem

In display devices with a single side driving structure, RC load nonuniformity and unsynchronized timings of scan and data signals lead to data charging ratio deviations, degrading display quality.

Innovation Solution

The display device employs multiple scan drivers with adjustable pulse widths controlled by a timing controller to synchronize scan signals across different pixel blocks, reducing RC load deviations and compensating for signal delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single side driving structure is used to reduce bezel size, then the device complexity is reduced, but RC load nonuniformity occurs and scan signal timing synchronization deteriorates

Engineering Contradiction:
Improvedriver structureVSAvoidsignal timing synchronization
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The display panel is divided into multiple pixel blocks (first pixel block, second pixel block, third pixel block) with each block driven by a dedicated scan driver (first scan driver, second scan driver, third scan driver). This segmentation allows independent timing control for each block, enabling precise compensation of RC load nonuniformity while maintaining the compact single side driving structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different scan drivers are configured with different pulse widths tailored to the specific RC load characteristics of each pixel block. The first scan driver supplies scan signals with a first pulse width, the second scan driver supplies scan signals with a second pulse width, and the third scan driver supplies scan signals with a third pulse width. This local quality adjustment compensates for timing variations in different regions of the display panel.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If different pulse widths are applied to different pixel blocks, then signal timing synchronization is improved, but the device complexity increases

Engineering Contradiction:
Improvesignal timing synchronizationVSAvoidscan driver configuration
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Multiple scan drivers are disposed at the same side of the display panel and merged into a unified single side driving structure. The first scan driver, second scan driver, and third scan driver are all positioned at one side, sharing the same physical space and control architecture, which reduces overall device complexity while enabling different pulse width configurations for each driver.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If multiple scan drivers with different pulse widths are used, then data charging ratio uniformity is improved, but the ease of manufacture deteriorates

Engineering Contradiction:
Improvedata charging ratio uniformityVSAvoiddriver assembly
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The scan drivers are designed with universal functionality to supply scan signals to multiple scan lines within their respective pixel blocks. Each scan driver can operate with different pulse width configurations while maintaining the same basic structure and control interface, simplifying the manufacturing process by using standardized components with adjustable parameters rather than completely different driver designs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3971875B1Display device having scan signals with adjustable pulse widths
Publication Date: 2026.04.15 SAMSUNG DISPLAY CO LTD
  • EP3971875B1 patent drawingFigure 1
  • EP3971875B1 patent drawingFigure 2A
  • EP3971875B1 patent drawingFigure 2B

AI summary

A display device includes a display panel including scan lines, first signal lines connected to the scan lines in a first pixel block, second signal lines connected to the scan lines in a second pixel block, third signal lines connected to the scan lines in a third pixel block; a first scan driver supplying a first output signal to the first signal lines based on a first sub-clock signal; a second scan driver supplying a second output signal to the second signal lines based on a second sub-clock signal; a third scan driver supplying a third output signal to the third signal lines based on and a third sub-clock signal; and a timing controller. Changes in pulse widths of the first to third output signals are different in one frame period.