Scan Driver Stage Architecture for Display Dead Space Reduction
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Solution Overview
Problem
In display devices with many elements, dead spaces where images are not displayed can increase due to the complexity of scan drivers, affecting image quality and efficiency.
Innovation Solution
A scan driver design incorporating multiple stages with specific transistor configurations and capacitor connections that allow for efficient output of scan signals based on node voltages, reducing dead spaces by implementing two stages as one, thereby optimizing signal output and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a scan driver with many elements is used to select pixels for data voltage writing, then the pixel selection capability is improved, but the dead space where images are not displayed increases
Solution Approach 1:
The scan driver is divided into multiple stages (first stage, second stage, etc.), where each stage handles a portion of the pixel selection task. This segmentation allows the driver to maintain high adaptability while reducing the dead space associated with a single large-scale driver by distributing functionality across smaller, more efficient units.
Solution Approach 2:
The patent introduces a multi-stage architectural dimension to the scan driver design. Instead of using a single planar driver structure, the solution stacks functional stages vertically or sequentially, transforming the driver's organizational structure from two-dimensional to multi-dimensional, thereby improving pixel selection capability without proportionally increasing dead space.
2Productivity
If multiple stages are implemented in the scan driver, then the scan signal output efficiency is improved, but the device complexity increases
Solution Approach 1:
Adjacent stages in the multi-stage scan driver are merged through shared components and integrated signal pathways. The output of one stage directly feeds into the next stage with minimal intermediate complexity, allowing the system to achieve high scan signal output efficiency while keeping the overall device complexity manageable through consolidation rather than isolation of stages.
Solution Approach 2:
Each stage in the multi-stage driver is designed with universal functionality to handle multiple tasks: signal generation, pixel selection, and output to data lines. This multi-functionality reduces the need for specialized components in each stage, thereby improving scan signal output efficiency without proportionally increasing device complexity.
Data Source
AI summary
A scan driver stage including: a first transistor including a gate connected to a first clock, a first electrode connected to a carry terminal, and a second electrode connected to a first node; a second transistor including a gate connected to a second clock, a first electrode connected to a carry terminal, and a second electrode connected to the first node; a third transistor including a gate connected to the first node and a first electrode connected to a second node; a fourth transistor including a gate connected to the second clock, a first electrode connected to power, and a second electrode connected to the second node; a fifth transistor including a gate connected to the first clock, a first electrode connected to power, and a second electrode connected to the second node; and an output outputting first and second scan signals based on first and second node voltages.