Clock Shaper Synchronization for High-Frequency Transition Fault Tests
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Solution Overview
Problem
Existing clock shaper circuits struggle to provide clock pulses at high frequencies (1.5 GHz to 2.0 GHz) for at-speed transition fault testing, leading to increased logic depth and synchronization issues.
Innovation Solution
A clock shaper circuit design that includes a synchronizing circuit with a logic depth of 2, a clock leaker circuit, and a multiplexer to provide clock pulses at the functional clock frequency of the integrated circuit, ensuring synchronized scan enable signals and minimizing wait cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing clock shaper circuits are used for at-speed transition fault testing, then clock pulses can be provided for testing, but the logic depth increases and synchronization issues occur at high frequencies (1.5 GHz to 2.0 GHz)
Solution Approach 1:
The clock shaper circuit is divided into distinct functional blocks: a synchronizing circuit that receives the scan enable signal and generates synchronized clock pulses, and a multiplexer that selects between different clock sources. This segmentation reduces the logic depth within each block while maintaining the overall testing functionality at high frequencies.
2Reliability
If existing clock shaper circuits are used for at-speed transition fault testing, then clock pulses can be provided for testing, but synchronization issues occur at high frequencies (1.5 GHz to 2.0 GHz)
Solution Approach 1:
The synchronizing circuit performs preliminary synchronization of the scan enable signal before generating clock pulses at the functional clock frequency. By pre-synchronizing the enable signal and using a synchronized clock source, the circuit maintains proper timing relationships and avoids synchronization issues even at high frequencies of 1.5 GHz to 2.0 GHz.
Data Source
AI summary
An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.