Scan-Enable Data Gating in Flip-Flops to Reduce Latch Toggling
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Solution Overview
Problem
Integrated circuits with millions of transistors face significant power consumption due to toggling of clock inputs in flip-flops, despite clock gating techniques, which do not effectively address primary latch toggling when the clock is disabled.
Innovation Solution
Implementing data gating in conjunction with clock gating to prevent both primary and secondary latch toggling by setting the input of the flip-flops to a constant logic level when the clock is disabled, using control circuitry to selectively disable the clock signal and input selection based on scan-enable and clock-enable controls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating is used to reduce dynamic power consumption, then power consumption is reduced, but primary latch toggling continues to occur when the clock is disabled
Solution Approach 1:
The flip-flop is segmented into two independent latches (primary and secondary) with separate control paths. The first latch receives the clock signal directly while the second latch receives a gated clock signal. This segmentation allows independent control of each latch, enabling the primary latch to be disabled when not needed, thereby preventing unnecessary toggling and reducing power consumption.
Solution Approach 2:
The control circuitry preliminarily determines whether the output of the flip-flop needs to be enabled before the clock signal reaches the latches. Based on this preliminary determination, the clock signal is conditionally gated before reaching the primary latch, preventing unnecessary toggling in advance and reducing dynamic power consumption before it occurs.
2Adaptability or versatility
If scan mode is implemented for testing, then testability is improved, but additional control circuitry and complexity are introduced
Solution Approach 1:
The flip-flop is designed with multi-functionality to operate in both functional mode and scan mode. The same control circuitry that gates the clock signal for power reduction is also used to enable scan mode operation. The scan input can be selectively coupled to the D input through the existing control logic, eliminating the need for separate dedicated scan control circuitry and reducing overall device complexity.
Solution Approach 2:
The scan control functionality is merged with the existing clock gating control circuitry. The control circuitry that determines whether to enable the output is also used to select between functional data input and scan data input. This merging of functions reduces the amount of additional control circuitry needed compared to traditional separate scan chain implementations.
3Use of energy by moving object
If both primary and secondary latch toggling is prevented, then power consumption is further reduced, but input selection complexity increases
Solution Approach 1:
The control circuitry is designed with multi-functionality to simultaneously perform clock gating, input selection, and latch disabling functions. The same control signals that enable/disable the output are also used to select between functional data input and scan data input, and to gate the clock signal to the primary latch. This universal control approach prevents unnecessary toggling in both latches while minimizing input selection complexity.
Solution Approach 2:
Multiple control functions are merged into a single unified control circuitry block. The clock gating function, the input selection function (between functional and scan data), and the latch disabling function are all combined and controlled by the same logic. This merging reduces the overall complexity compared to implementing separate control circuits for each function.
Data Source
AI summary
An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.