Low-Power Scan Flip-Flop Using OAI/AOI Clock Logic
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Solution Overview
Problem
Conventional scan flip-flops in integrated circuits require large area and consume additional power due to the use of transmission gates for generating complementary clock signals, increasing design complexity and power consumption.
Innovation Solution
The implementation of OR-AND-Inverter (OAI) and AND-OR-Inverter (AOI) logic gates in scan flip-flop circuits eliminates the need for transmission gates, reducing power consumption and design complexity by using complex logic gates to generate clock signals, thereby improving performance and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transmission gates are used to generate complementary clock signals in scan flip-flops, then the clock signal generation function is achieved, but the area occupied increases and power consumption increases
Solution Approach 1:
The patent removes the transmission gate component from the scan flip-flop circuit entirely. Instead of using transmission gates to generate complementary clock signals, the invention uses a different architectural approach where the clock signal is distributed directly to multiple latch circuits without requiring transmission gates, thereby eliminating the area overhead associated with transmission gates while maintaining the necessary clock signal generation function
Solution Approach 2:
The patent makes the clock signal serve multiple functions simultaneously by distributing it to multiple latch circuits (first latch, second latch, third latch, fourth latch) without requiring separate transmission gates for each. The same clock signal path serves all latch circuits, eliminating redundant components and reducing overall circuit area while maintaining reliable clock signal generation for all storage elements
2Reliability
If transmission gates are used to generate complementary clock signals in scan flip-flops, then the clock signal generation function is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the transmission gate component that causes excessive power consumption. By eliminating transmission gates from the clock signal distribution path, the invention removes the primary source of dynamic power consumption in conventional scan flip-flops, achieving significant power savings while maintaining reliable clock signal generation through alternative circuit architecture
Solution Approach 2:
Instead of using transmission gates to enable clock signal passage (the conventional approach), the patent inverts the approach by using always-on clock signal distribution combined with control signals applied directly to latch enable inputs. This inversion eliminates the switching losses inherent in transmission gate operation while achieving the same functional result of controlled clock signal distribution
3Reliability
If transmission gates are used in scan flip-flops, then clock signal distribution is achieved, but design complexity increases
Solution Approach 1:
The patent removes transmission gates and their associated control logic from the scan flip-flop design, significantly simplifying the circuit architecture. By eliminating these complex components, the invention reduces design complexity, decreases the number of transistors required, and simplifies the overall circuit layout while maintaining effective clock signal distribution to all necessary latch circuits through a simpler direct distribution approach
Data Source
AI summary
A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.