Scan Flip-Flop Circuit Reducing Clock Tree Power
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Solution Overview
Problem
The increasing power consumption of clock trees in integrated circuits, particularly in portable devices, due to the growing load presented by clocked circuits, necessitates a solution to manage this load effectively.
Innovation Solution
The implementation of a scan flip-flop circuit with a scan input sub-circuit and a selection sub-circuit that generates complementary scan input signals and shares clock and scan enable buffers between multiple flip-flops, reducing the load on the clock tree and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of buffers in the clock tree is increased to manage the load presented by clocked circuits, then the timing characteristics of the clock signal are maintained, but the power consumption of the clock tree increases
Solution Approach 1:
The clock tree is segmented into multiple buffer stages, where buffers are strategically placed at different levels of the clock distribution hierarchy. This segmentation allows the clock signal to be distributed efficiently across different clock domains while maintaining timing characteristics and reducing the fanout burden on individual buffers, thereby lowering overall power consumption.
Solution Approach 2:
Different buffer configurations and strengths are applied to different regions of the clock tree based on local loading requirements. Critical clock paths receive stronger buffering to maintain timing, while non-critical paths use weaker buffers to minimize power consumption. This localized optimization resolves the contradiction between maintaining timing characteristics and reducing power usage.
2Use of energy by moving object
If the fanout of each buffer is limited to reduce power consumption, then the power consumption decreases, but the ability to drive large loads is reduced
Solution Approach 1:
The clock distribution network is divided into multiple hierarchical levels with buffers at each level driving a limited number of downstream buffers. This segmentation ensures that individual buffers have limited fanout (reducing power consumption) while the collective buffer system can drive large total loads through the hierarchical structure.
Solution Approach 2:
Multiple buffer outputs are merged to drive a single downstream load, and multiple downstream loads are served by merging buffer capabilities at higher hierarchical levels. This merging approach allows the system to maintain limited individual fanout while achieving the necessary total drive capability for large loads.
Data Source
AI summary
A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.