Scan Flip-Flop Data Retention Without Propagation Delay
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Solution Overview
Problem
During structural testing of system-on-chips (SoCs), functional data stored in scan flip-flops is lost due to overwrite, requiring significant reset time and degrading SoC performance, as existing solutions with additional multiplexers for data retention introduce delays in functional data propagation.
Innovation Solution
A scan flip-flop design incorporating a selection circuit and multiple latches that selectively outputs functional data, reference data, or scan data based on control signals, allowing data retention without introducing delays in the functional data propagation path during structural testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional multiplexer is added to each scan flip-flop for data retention, then data retention during structural testing is improved, but delay in functional data propagation is introduced
Solution Approach 1:
The patent divides the data path into separate segments: the additional multiplexer for data retention is placed only in the test data path, while the functional data path remains separate and unaffected. This segmentation allows data retention functionality to be added without introducing delays to functional operations.
Solution Approach 2:
The patent introduces a test data path as an intermediary channel that operates separately from the functional data path. This intermediary path includes the additional multiplexer and latches, allowing test operations to perform data retention while functional operations proceed through the original path without delay.
2Productivity
If functional data is overwritten during structural testing, then data retention is improved, but reset time increases significantly
Solution Approach 1:
The patent performs preliminary action by capturing functional data into dedicated retention latches before structural testing begins. This preliminary capture ensures data is preserved in advance, eliminating the need for time-consuming reset operations after testing completes.
Solution Approach 2:
The patent discards the overwritten functional data in the original latches during testing, while simultaneously recovering and preserving the data in separate retention latches. This discarding and recovering mechanism allows testing to proceed without affecting the preserved data, eliminating post-testing reset requirements.
Data Source
AI summary
A scan flip-flop includes a selection circuit, a primary latch, a secondary latch, and a data retention latch. The selection circuit selects and outputs one of functional data, first reference data, scan data, and first control data as second reference data. The primary latch receives the second reference data and outputs third reference data, whereas the secondary latch receives the third reference data and outputs second control data. The second control data is then provided to a subsequent scan flip-flop of a scan chain. The data retention latch receives one of the third reference data and the second control data, and outputs and provides the first reference data to the selection circuit. The first reference data corresponds to functional data retained in the scan flip-flop during a structural testing mode associated with the scan chain.