Scan Output Flip-Flop Circuit for Low-Power Delay Chains
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Solution Overview
Problem
Scan output flip-flops in scan chains experience unnecessary power consumption due to operational buffers in delay chains, and existing solutions occupy significant area or induce errors.
Innovation Solution
A scan output flip-flop design incorporating a selection circuit, control circuit, and scan-out stage circuit with transistors, which selectively generates a fixed scan-out signal, reducing power consumption and area occupancy by controlling signal transmission based on test and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a scan-out circuit is added to gate the scan-out signal at a fixed level in normal mode, then power consumption of delay chains is reduced, but the scan-out circuit occupies larger area and has low driving capability
Solution Approach 1:
The patent combines the scan-out gating function with the existing output buffer circuitry of the flip-flop. The scan-out signal is gated by controlling the output buffer's enable signal, eliminating the need for a separate scan-out circuit. This merging approach reduces area occupancy while maintaining the power-saving effect of gating the scan-out signal at a fixed level in normal mode.
Solution Approach 2:
The output buffer circuit is designed to serve multiple functions: it drives both the normal data output signal and the scan-out signal. By controlling the enable signal of this universal buffer, the circuit can gate the scan-out signal to save power during normal operation while maintaining full driving capability when needed for scan operations or outputting data signals.
2Loss of energy
If a scan-out circuit is added to gate the scan-out signal at a fixed level in normal mode, then power consumption of delay chains is reduced, but the scan-out circuit induces ERC errors
Solution Approach 1:
By merging the scan-out gating function into the existing output buffer circuit, the patent ensures that the gating control is implemented through a proven, reliable circuit path. This approach avoids introducing new potential failure points and ERC errors that would arise from adding a separate scan-out circuit with its own control logic and signal paths.
Solution Approach 2:
The output buffer circuit inherently possesses the capability to gate its own output signal through its enable control. By utilizing this self-service capability, the circuit can gate the scan-out signal without requiring external control circuitry, thereby maintaining reliability and avoiding ERC errors while achieving power savings.
3Reliability
If buffers in delay chains operate continuously in normal mode, then signal integrity is maintained, but unnecessary power consumption increases
Solution Approach 1:
The patent extracts the scan-out signal from the main data path at the flip-flop output stage, before it enters the delay chain. By gating this extracted scan-out signal at a fixed level in normal mode, the delay chain buffers do not need to operate continuously, thereby reducing power consumption while the main data path continues to maintain signal integrity through its dedicated buffer circuitry.
Solution Approach 2:
The patent segments the output signal path into two separate paths: the main data output path that maintains signal integrity through continuous buffer operation, and the scan-out path that is gated to save power. This segmentation allows the system to maintain signal integrity where needed while reducing power consumption in the scan-out function during normal operation.
Data Source
AI summary
A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.