Master-Slave Scan Flip-Flop Layout for Low-Power Operation
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving both low power consumption and high performance, particularly in flip-flop circuits and latches, which are crucial for mobile devices, as they often consume increasing power and affect operating speeds.
Innovation Solution
A semiconductor device incorporating a master-slave flip-flop design with a scan input circuit, master and slave latches, and inverters that selectively output signals based on scan enable signals, reducing power consumption by minimizing unnecessary operations during non-scan test modes and embedding inverters for delay, thereby reducing area and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional flip-flop circuits and latches are used to ensure appropriate performance, then operating speed is maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic operation mode switching between scan test mode and normal operation mode. The scan input circuit dynamically selects between scan input signal and normal data input signal based on scan enable signal, allowing the flip-flop to adapt its behavior to different operational requirements, thereby achieving low power consumption in normal mode while maintaining performance when needed
Solution Approach 2:
The patent employs periodic clock signal phases (first clock signal and second clock signal) to control the master and slave latches alternately. This periodic action allows the circuit to enter low-power states during non-active phases while maintaining data storage functionality, reducing overall power consumption without sacrificing operating speed when clocked
2Adaptability or versatility
If more components are added to improve functionality, then versatility increases, but device area increases
Solution Approach 1:
The patent designs the scan input circuit to serve multiple functions: it acts as a data input circuit during normal operation and as a scan test input circuit during test mode. The same physical circuit structure and components are utilized for both purposes, eliminating the need for separate dedicated scan test circuits and thereby reducing overall device area while maintaining functional versatility
Solution Approach 2:
The patent merges the scan test functionality with the normal data input functionality by using shared circuit components including the scan input circuit, master latch, slave latch, and output circuitry. This consolidation allows a single integrated structure to perform both test and operational functions, reducing the total component count and device area
Data Source
AI summary
A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.