Scan Flip-Flop Loopback Circuit for Memory Test Routing
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Solution Overview
Problem
Designing circuits with memories that are subjected to scan tests is challenging due to the difficulty in covering the front-stage and back-stage circuits effectively, especially when clock speeds are high and the number of memories is large, leading to increased complexity in routing and area occupation.
Innovation Solution
The circuit employs scan flip-flops with specific voltage-level dependent operations and loopback paths during scan modes, eliminating the need for a bypass circuit between the front-stage and back-stage of the memory, which simplifies signal transmission and reduces routing complexity by using multiplexers and NOT gates to form loops that do not pass through certain scan FFs during the capture phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bypass circuit is added between the front-stage and back-stage of the memory to improve scan test coverage, then the test coverage is improved, but the routing complexity and area occupation increase
Solution Approach 1:
The patent extracts the bypass circuit functionality from the traditional scan chain architecture. Instead of adding a separate bypass circuit between front-stage and back-stage scan FFs, the invention removes the memory from the scan path entirely during scan operations. The scan FFs directly connect to each other forming a simplified scan chain that bypasses the memory, achieving full scan coverage without the complexity of additional routing or bypass components.
Solution Approach 2:
The patent implements dynamic control of the scan chain configuration using control signals. The scan FFs can dynamically switch between two modes: (1) normal operation mode where data flows through the memory, and (2) scan test mode where scan data flows directly through the scan chain without entering the memory. This dynamic reconfiguration allows the same hardware to serve both functional and test purposes without requiring permanent bypass routing.
2Productivity
If the clock speed is increased to improve productivity, then the processing speed is improved, but the difficulty of implementing scan test coverage increases
Solution Approach 1:
The patent segments the data path into two independent channels: (1) the functional data path that goes through the memory for normal operation, and (2) the scan test path that goes directly through the scan FFs for testing. This segmentation allows the scan chain to operate independently of the memory speed, enabling high-speed scanning without being constrained by memory access times. The scan chain can be clocked at its own optimal frequency separate from the functional clock.
Data Source
AI summary
The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.