Scan Flip-Flop Circuit With Integrated Mode Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flip-flop circuits face challenges in achieving faster operation, reduced power consumption, and smaller circuit area due to signal inversions and the need for additional components like multiplexers and transmission gates.
Innovation Solution
The flip-flop circuit design reduces signal inversions by merging or replacing the scan multiplexer, utilizing symmetric cross-coupled Or-And-Inverter (OAI) and And-Or-Inverter (AOI) logic gates, and eliminating the need for a conventional multiplexer, thereby reducing transistor count and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional flip-flop circuits use multiplexers and transmission gates for mode switching, then the circuit can achieve versatility in operation modes, but the device complexity and component count increase
Solution Approach 1:
The patent merges the scan mode and normal mode functionality into a unified circuit structure. The same cross-coupled OAI/AOI gate configuration handles both scan operation (when scan enable is active) and normal D-flip-flop operation (when scan enable is inactive), eliminating the need for separate multiplexers for each mode.
Solution Approach 2:
The circuit employs universal logic gates (OAI and AOI) that can perform multiple functions. These gates serve as both scan path elements and data path elements depending on the scan enable signal state, allowing a single circuit configuration to fulfill multiple operational roles without requiring mode-specific components.
2Reliability
If conventional flip-flop circuits include multiple signal inversions, then the logic functionality is achieved, but the circuit speed decreases
Solution Approach 1:
The patent uses asymmetric cross-coupled gate configurations where one gate is an Or-And-Inverter (OAI) and the other is an And-Or-Inverter (AOI). This asymmetric design allows the circuit to achieve the necessary logic inversion functionality while minimizing the number of signal inversions compared to symmetric conventional designs, thereby improving propagation speed.
3Adaptability or versatility
If conventional flip-flop circuits use standard multiplexer designs, then the mode selection functionality is achieved, but the power consumption increases
Solution Approach 1:
The patent extracts and eliminates the dedicated multiplexer components from the circuit. Instead of using separate multiplexer blocks for mode selection, the design integrates mode switching functionality directly into the cross-coupled gate structure, removing the power-consuming multiplexer elements while preserving mode selection capability through the scan enable signal.
Data Source
AI summary
A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.