Scan Register Circuit for Fail Bit Count and Position Search
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Solution Overview
Problem
Flash memory devices face challenges in accurately determining the number and position of fail bits to effectively correct errors, which affects data integrity and reliability.
Innovation Solution
A scan register circuit with a fail bit count operation and position search operation is implemented, comprising a scan register array with multiple scan chain units and a fail bit output circuit to determine the number and position of fail bits based on operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a scan register circuit is used to determine fail bit information, then measurement precision of fail bit detection is improved, but device complexity increases
Solution Approach 1:
The scan register circuit is divided into multiple scan chain units, each responsible for monitoring a specific portion of the memory cell array. This segmentation allows parallel processing of fail bit detection across different regions, improving measurement precision while distributing the complexity across multiple simpler units rather than one complex monolithic circuit.
Solution Approach 2:
The scan register circuit performs multiple functions: it determines both the number of fail bits and their positions, and can operate in different modes (fail bit count mode and position search mode). This multi-functionality consolidates what would otherwise require separate circuits into a single versatile unit, improving measurement precision without proportionally increasing device complexity.
2Measurement precision
If fail bit count operation is performed to determine the number of fail bits, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The scan registers are pre-configured with scan chain units that are ready to simultaneously capture fail bit information from multiple memory cell array regions. This preliminary arrangement allows the circuit to perform comprehensive fail bit counting in parallel across all regions during a single operation cycle, improving measurement precision without significant time penalty.
Solution Approach 2:
The scan register circuit operates in periodic cycles, alternating between fail bit count mode and position search mode. During fail bit count mode, all scan chain units simultaneously evaluate fail bit status, and the results are aggregated. This periodic operation allows efficient batch processing of fail bit information, improving measurement precision while minimizing detection time through parallel evaluation across multiple cycles.
3Measurement precision
If position search operation is performed to find fail bit positions, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The scan register circuit dynamically switches between operational modes based on needs: fail bit count mode for determining the number of errors, and position search mode for locating specific fail bits. This dynamic adaptability allows the system to optimize measurement precision for position detection while maintaining overall productivity by using faster fail bit count operations when only error quantity is needed, avoiding the time-consuming position search.
Solution Approach 2:
The circuit can perform partial position search by utilizing the fail bit count information to narrow down the search scope. Instead of systematically checking all memory cell positions, the circuit uses the fail bit count results to identify regions with errors, then performs position search only in those specific regions. This partial action approach improves measurement precision for position detection while significantly reducing the time required compared to a complete search of all positions.
Data Source
AI summary
A memory device includes a memory cell array configured to store data, a page buffer circuit configured to store data in the memory cell array or read data stored in the memory cell array, and a scan register circuit configured to receive a pass/fail result of data from the page buffer circuit and store the pass/fail result in a plurality of scan registers. The scan register circuit obtains information about the scan register where the fail result is stored through a scan operation, and uses the information about the scan register where the fail result is stored to determine the number of fail bits and/or a position index indicating the position of the fail bits according to the operation mode.


