Scan Shift Clock Staggering for Peak Power Reduction
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Solution Overview
Problem
Scan shift operations in integrated circuit testing face challenges with high peak power issues due to high toggling rates and logic activity during scan shift mode, leading to voltage drops and potential chip failures, which necessitate slower clock speeds and longer test times.
Innovation Solution
The implementation of partition level shift clock staggering, where scan data is routed serially to multiple partitions with staggered clock signals, allowing each partition to shift data at a different time, reducing peak power and enabling higher clock speeds during scan shift operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan shift operations are run at higher clock speeds to reduce test time, then productivity is improved, but peak power consumption increases causing voltage drops and chip failures
Solution Approach 1:
The patent divides the scan chain into multiple segments or groups, and applies clock staggering to different segments. This segmentation allows different portions of the scan chain to operate at different times, reducing the peak power consumption while maintaining high clock speeds for overall test productivity.
Solution Approach 2:
The patent implements periodic clock staggering where clock signals are applied in a staggered periodic manner to different scan chain segments. This periodic action distributes the power consumption over time, preventing peak power spikes while enabling sustained high-speed operation.
2Productivity
If all flip-flops switch simultaneously during scan shift to maximize speed, then productivity is improved, but voltage drop from rail resistance increases causing incorrect behavior
Solution Approach 1:
The patent segments the scan chain and applies staggered clocking to different segments, so that not all flip-flops switch simultaneously. This reduces the peak current demand on power rails, minimizing voltage drops and ensuring reliable operation while maintaining high scan shift speeds.
Solution Approach 2:
The patent applies different clock timing characteristics to different local segments of the scan chain. Each segment receives clock signals with appropriate staggering, creating local quality variations in clock timing that prevent simultaneous switching across the entire chip, thereby ensuring correct operation.
3Power
If clock speed is reduced to minimize peak power issues, then power consumption is controlled, but test time increases
Solution Approach 1:
The patent uses periodic clock staggering that allows the scan chain to operate at high clock speeds in a distributed manner. The periodic application of staggered clocks to different segments enables high-speed operation without sustained peak power consumption, thus reducing test time while controlling power.
Solution Approach 2:
The patent implements dynamic clock staggering where the clock timing is adaptively adjusted for different scan chain segments. This dynamic approach allows the system to maintain high clock speeds when needed while distributing power consumption, optimizing both test time and power consumption.
4Productivity
If high toggling rates are used during scan shift to reduce test time, then productivity is improved, but dynamic power consumption exceeds design limits causing heat dissipation issues
Solution Approach 1:
The patent segments the scan chain and applies staggered clocking to distribute the toggling activity across different time periods. This segmentation reduces the peak dynamic power consumption and heat dissipation while maintaining high overall test speed by keeping the scan chains operating at high frequencies in a distributed manner.
Data Source
AI summary
A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, where each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, where each partition receives a respective one of the plurality of second clock signals and where the plurality of second clock signals are staggered where each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.