Scan Test Multiplexer Circuit for High-Coverage Digital Testing
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Solution Overview
Problem
Existing test circuits for digital circuits have limited test coverage, typically achieving less than 70%, and require additional multiplexers that increase chip surface area and power consumption to reach higher coverage, falling short of the desired 99% target.
Innovation Solution
An electronic test circuit with a multiplexer having additional output NSZ that receives the signal from the first input when the test mode is activated and sets it to zero when deactivated, coupled with a scan flip-flop to increase test coverage to over 99% while minimizing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional multiplexers are added to increase test coverage, then test coverage is improved, but chip surface area and power consumption increase
Solution Approach 1:
The multiplexer is designed to perform multiple functions: it operates in both functional mode (connecting first input to first output) and test mode (connecting third input to first output), while simultaneously providing both first and second outputs. This multi-functionality eliminates the need for separate dedicated test multiplexers, thereby increasing test coverage without proportionally increasing chip area.
Solution Approach 2:
The invention adds a new dimension to the multiplexer by introducing a second output in addition to the traditional first output. This allows the same multiplexer structure to serve dual purposes: the first output handles functional signals while the second output provides test signal access, effectively doubling the utility of the component without linearly increasing area consumption.
2Reliability
If additional multiplexers are added to increase test coverage, then test coverage is improved, but power consumption increases
Solution Approach 1:
The multiplexer is designed to perform multiple functions: it operates in both functional mode (connecting first input to first output) and test mode (connecting third input to first output), while simultaneously providing both first and second outputs. This multi-functionality eliminates the need for separate dedicated test multiplexers, thereby increasing test coverage without proportionally increasing power consumption.
3Reliability
If the multiplexer connects third input to first output during test mode, then test signal access is improved, but functional signal access is lost
Solution Approach 1:
The multiplexer's output functionality is segmented into two separate outputs: the first output handles functional mode operations while the second output handles test mode operations. During test mode, the third input connects to the first output for test signal access, while the second output simultaneously provides access to the functional signal from the first input, ensuring both test and functional signals remain accessible concurrently.
Solution Approach 2:
The invention adds a new dimension to the multiplexer by introducing a second output in addition to the traditional first output. This allows the same multiplexer structure to serve dual purposes: the first output handles functional signals while the second output provides test signal access, effectively doubling the utility of the component without linearly increasing area consumption.
Data Source
AI summary
The present description concerns an electronic circuit for testing a digital signal, comprising a signal selection circuit having a first input configured to receive a signal from the digital circuit to be tested, a second input configured to receive a test mode activation signal, a third input, a first output configured to receive a state of the third input when the second input is activated and a state of the first input when the second input is deactivated, and a second output configured to receive a state of a signal present on the first input or to be set to zero when the second input is respectively activated or deactivated.


