Scannable Storage Circuit Timing for Lower Set-Up Delay

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Solution Overview

Problem

The additional delay introduced by scan flip-flops in synchronous circuits due to added testing circuitry reduces the maximum operating frequency and increases the set-up time, limiting the performance of the circuit.

Innovation Solution

A method and system for control signal synchronization in scannable storage circuits, where each storage circuit includes a scan enable signal, an input transmission gate, and a loop transmission gate that synchronously closes a hold loop when the input transmission gate is opened, reducing set-up time and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If scan flip-flops are used to enable testing functionality, then testing capability is improved, but propagation delay increases and maximum operating frequency decreases

Engineering Contradiction:
Improvetesting capabilityVSAvoidmaximum operating frequency
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements dynamic control of transmission gates based on the scan enable signal state. When in functional mode, the hold loop transmission gate remains closed to provide a direct path. When in scan mode, the transmission gate opens to allow scan data input. This dynamic switching optimizes performance for each operational mode separately.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the data path into two separate physical paths: one for functional data input and another for scan data input. Each path has its own optimized transmission gate control, allowing independent optimization of each path's performance characteristics without compromising the other.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If scan flip-flops with additional testing circuitry are used, then testing capability is improved, but set-up time increases

Engineering Contradiction:
Improvetesting capabilityVSAvoidset-up time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent prepares the hold loop transmission gate control signal in advance by synchronizing it with the input transmission gate opening. This preliminary action ensures that when the input transmission gate opens to accept new data, the hold loop transmission gate is already in the correct state to receive and hold the data without additional delay.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a synchronized control signal as an intermediary that coordinates the opening of the input transmission gate with the state of the hold loop transmission gate. This intermediary signal ensures proper timing alignment between the two gates, preventing setup time violations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If additional circuitry for scan enable signal is added, then testing capability is improved, but power consumption increases

Engineering Contradiction:
Improvetesting capabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent uses periodic clock signals to control the transmission gates, enabling them only during the appropriate phases of the clock cycle. This periodic activation reduces power consumption compared to continuously enabled gates, as the gates remain in high-impedance state during inactive periods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent discards the use of the hold loop transmission gate during functional operation by keeping it closed, and recovers its use during scan operation by opening it. This selective usage pattern ensures that the additional circuitry consumes minimal power during normal operation while being fully functional during testing.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS7543205B2Control signal synchronization of a scannable storage circuit
Publication Date: 2009.06.02 TEXAS INSTRUMENTS INC
  • US7543205B2 patent drawing
  • US7543205B2 patent drawing
  • US7543205B2 patent drawing

AI summary

A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit. Each of the storage circuits may include an input transmission gate to apply any one of a data input and a scan input to a storage element of the storage circuit based on an input circuitry that considers the state of the scan enable signal and a timing signal of a clock associated with the storage element. In addition, a control signal in a master latch of the storage element may synchronously close a hold loop in the master latch when the input transmission gate is opened upon the timing signal of the clock transitioning to a different state.