Scatter List Caching Engine DMA Transfer Optimization
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Solution Overview
Problem
Network and storage array test devices face inefficiencies in receiving high-speed data due to the limitations of using the host CPU for data transfer, and existing methods for providing scatter list information to DMA controllers are slow and resource-intensive, particularly when cache refilling is required.
Innovation Solution
Implementing a scatter list caching engine that caches metadata associated with partially used scatter list entries, allowing the DMA controller to efficiently write data to host system memory by providing cached metadata, thereby reducing the need for frequent writes and reads from host system memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If scatter list entries are cached in protocol offload engine memory, then DMA transfer speed is improved, but cache memory is frequently exhausted requiring refilling
Solution Approach 1:
The scatter list cache is divided into multiple cache banks (first cache bank, second cache bank, etc.) that can be independently managed. When one cache bank is exhausted, the system can switch to another cache bank, allowing continuous operation without stalling for cache refilling. This segmentation resolves the contradiction by maintaining high transfer speed while effectively increasing the total cache capacity through parallel cache structures.
2Quantity of substance
If scatter list entries are written back to host system memory after partial use, then memory usage is optimized, but read/write operations slow down performance
Solution Approach 1:
The system pre-loads scatter list entries into multiple cache banks before they are needed for DMA transfers. By having multiple cache banks pre-filled with scatter list entries, the protocol offload engine can continue operating at high speed without stalling for memory refills. This preliminary action resolves the contradiction by maintaining both memory efficiency and high performance through advance preparation.
3Measurement precision
If host CPU controls data receiving into memory, then data transfer accuracy is maintained, but transfer speed is insufficient for high line rates
Solution Approach 1:
A DMA controller is introduced as an intermediary between the protocol offload engine and host system memory. The DMA controller handles high-speed data transfer operations, freeing the host CPU to perform other tasks while maintaining accurate data transfer through dedicated hardware control. This intermediary resolves the contradiction by enabling both high transfer speed and data accuracy through specialized hardware assistance.
Data Source
AI summary
Methods, systems, and computer readable media for caching and using scatter list metadata to control DMA receiving of network protocol data are described. According to one method, metadata associated with partially used scatter list entries is cached in memory of a scatter list caching engine. Data to be written to host system memory is received. The scatter list caching engine provides the metadata associated with partially used scatter list entries to a DMA controller to control the DMA writing of the data into host system memory.