Integrated SCR and Diode ESD Protection for High-Speed Signal Nodes
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Solution Overview
Problem
Large-scale System-on-a-Chip (SoC) electronic systems face challenges in providing effective protection against transient electrical events like electrostatic discharge (ESD) without degrading signal integrity, particularly due to complexity in implementing distributed on-chip protection, which can lead to damage such as gate oxide punch-through and surface charge accumulation.
Innovation Solution
The development of silicon controlled rectifier (SCR) and diode structures integrated into a common circuit layout, operating between a signal node and a power low supply node, providing both forward and reverse blocking voltages to protect against positive and negative polarity ESD events, while maintaining signal integrity and reducing capacitance and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distributed on-chip protection is implemented, then ESD protection capability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple protection functions (forward ESD protection, reverse ESD protection, and signal routing) into a single integrated circuit layout. The SCR structure and diode structure share common elements such as the n-type semiconductor region, p-type semiconductor region, and substrate, eliminating the need for separate protection circuits and reducing overall device complexity while maintaining comprehensive ESD protection capability.
2Reliability
If protection devices are added, then ESD protection is improved, but signal integrity deteriorates
Solution Approach 1:
The protection device is designed to have frequency-dependent characteristics where it provides effective ESD protection for transient events while maintaining high signal integrity for normal operating frequencies up to 10 GHz. The SCR and diode structures are configured to have low capacitance and controlled impedance characteristics that minimize signal degradation in the operating bandwidth while providing robust protection against electrical overstress.
3Area of stationary object
If protection structures are integrated, then device area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The integrated protection device is divided into functionally distinct segments including the SCR protection structure, the diode protection structure, and their interconnecting elements. Each segment can be independently optimized and fabricated using standard CMOS process steps, reducing the overall manufacturing precision requirements while achieving compact integration. The segmented design allows for independent layout optimization of each protection function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects high-speed signal nodes and analog-to-digital converters by providing robust ESD protection with minimal impact on signal integrity, reducing capacitance, and maintaining low standing leakage, suitable for high-frequency applications up to 10 GHz.
Implementation Method 1
The first p-type diffusion region, the first n-type semiconductor region, the first p-type semiconductor region, and the first n-type diffusion region are configured to operate as a first silicon controlled rectifier (SCR) in a first electrical path between the second node and the first node
Implementation Method 2
The second n-type diffusion region and the second p-type semiconductor region are configured to operate as a diode in a second electrical path between the power low supply network and the signal node
Data Source
AI summary
Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.