SCR ESD Protection Structure With Multiple Holding Current Paths
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Solution Overview
Problem
Integrated circuits face damage from random electrostatic discharge (ESD) events due to the lack of effective protection mechanisms, particularly in silicon-controlled rectifiers (SCRs) which can remain clamped in a conducting state even after the ESD current drops below the holding current, leading to potential latch-up issues.
Innovation Solution
A structure for a silicon-controlled rectifier is designed with specific doped regions and wells in a semiconductor substrate, including a first and second well with opposite conductivity types, and doped regions positioned laterally between them, forming multiple current paths to enhance holding voltage and current, thereby improving latch-up immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SCR structure is used for ESD protection, then the device can conduct ESD current to ground, but the SCR may remain clamped in low-impedance state even after ESD current drops below holding current, causing latch-up issues
Solution Approach 1:
The SCR structure is segmented into multiple independent doped regions (first doped region in first well, second doped region in first well, third doped region in second well) with distinct current paths. This segmentation allows each region to contribute to holding current, ensuring the device can reliably return to quiescent state without unwanted latch-up conditions.
2Reliability
If the SCR structure is simplified for easier manufacture, then fabrication cost decreases, but the holding voltage and current levels may be insufficient to prevent latch-up
Solution Approach 1:
The patent implements local quality by creating specific doped regions with distinct conductivity types in specific locations: a first doped region with first conductivity type in a first well, a second doped region with second conductivity type in the first well, and a third doped region with third conductivity type in a second well. This localized doping strategy enhances holding voltage and current levels at critical locations without requiring complex global structural modifications, thereby maintaining manufacturability while improving reliability.
3Reliability
If multiple current paths are introduced to enhance holding current, then latch-up immunity improves, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into a unified SCR structure: the first doped region, second doped region, and third doped region are integrated within respective wells to form multiple current paths simultaneously. This merging approach creates enhanced latch-up immunity through multiple holding current paths while avoiding the complexity of separate discrete components, as all regions work together within a single integrated device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure provides enhanced latch-up immunity and improved performance by allowing multiple current paths during ESD events, reducing on-resistance and maintaining high holding voltage and current levels.
Implementation Method 1
a first well and a second well in a semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type
Implementation Method 2
An ESD event refers to an unpredictable electrical discharge of a positive or negative current over a short duration and during which a large amount of current is directed to the integrated circuit
Implementation Method 3
a first doped region that has a portion in the first well, and a second terminal including a second doped region that has a portion in the first well and a third doped region in the second well. The first doped region and the second doped region have the second conductivity type, the third doped region has the first conductivity type
Data Source
AI summary
Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes a first well and a second well in a semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. The structure further includes a first terminal having a doped region that has a portion in the first well, and a second terminal including a second doped region that has a portion in the first well and a third doped region in the second well. The first and second doped regions have the second conductivity type, the third doped region has the first conductivity type, and the second doped region is positioned in a lateral direction between the first doped region and the third doped region.