SCR Gate Electrode Segmentation for ESD Protection
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Solution Overview
Problem
Silicon controlled rectifiers face challenges in high-speed electrostatic discharge protection due to high parasitic gate-to-anode capacitance and the difficulty in independently regulating holding voltage without increasing device size.
Innovation Solution
The design incorporates a substrate with n-wells and p-wells, a field oxide layer, and gate electrode layers with dielectric layers, allowing for separate control of the silicon controlled rectifier and independent regulation of holding voltage without increasing device size, while reducing parasitic capacitance and enhancing current handling capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon controlled rectifier is used for electrostatic discharge protection, then protection capability is improved, but parasitic gate to anode capacitance increases which limits high speed performance
Solution Approach 1:
The gate electrode is segmented into multiple portions with different configurations. The first gate electrode portion has a first configuration while the second gate electrode portion has a second configuration, allowing independent optimization of different gate regions to reduce parasitic capacitance while maintaining ESD protection capability.
Solution Approach 2:
Different portions of the gate electrode are given different local properties through varying their configurations. The first and second gate electrode portions have distinct configurations that optimize local electrical characteristics, reducing overall parasitic capacitance while maintaining protection function.
2Reliability
If the device size is increased to independently regulate holding voltage, then holding voltage regulation is improved, but device footprint increases
Solution Approach 1:
The gate electrode structure serves multiple functions: it provides electrostatic discharge protection, enables independent holding voltage regulation, and maintains compact device footprint. The multi-portion gate configuration allows simultaneous achievement of these functions without requiring separate dedicated structures.
Solution Approach 2:
The first and second gate electrode portions are combined into a single integrated gate electrode structure that performs both ESD protection and holding voltage regulation functions, eliminating the need for separate devices and reducing overall footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a silicon controlled rectifier with low parasitic capacitance, high holding voltage, and high current handling capability, effectively protecting against electrostatic discharge while maintaining a compact device footprint.
Implementation Method 1
high parasitic gate to anode capacitance in silicon controlled rectifier devices may limit their use in high speed input/output protection
Data Source
AI summary
A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.