Scribe Structure with Liner for Low-k Film Crack Suppression
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Solution Overview
Problem
Low-k insulating materials in semiconductor devices, such as silicon oxycarbide and silicon carbonitride, exhibit weak thermo-mechanical characteristics, leading to adhesion issues and brittleness, which result in cracks during the dicing process, reducing yield and causing discontinuous conductive seed layers due to concave edge surfaces.
Innovation Solution
The implementation of a cover layer and liners, including dielectric materials like silicon nitride and silicon carbide, to cover edge surfaces of low-k films, providing support and suppressing cracks, and the deposition of a conductive seed layer in a seamless manner to facilitate continuous electroplating of conductive pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low-k insulating material is used to reduce parasitic capacitance, then high speed operations are achieved, but adhesion to conductive layers deteriorates and cracks occur during dicing
Solution Approach 1:
A liner layer is introduced as an intermediary between the low-k insulating material and the conductive layer. This liner acts as a mediator that provides both mechanical support to prevent cracks in the brittle low-k material and ensures good adhesion to the conductive layer, thereby resolving the contradiction between achieving high speed operations and maintaining reliability
Solution Approach 2:
The structure employs a composite material system consisting of multiple layers including the low-k insulating material, liner layer, and cap layer. Each material is selected for its specific properties: the low-k material for electrical performance, the liner for mechanical support and adhesion, and the cap for protection. This composite approach allows simultaneous achievement of high speed and reliability
2Reliability
If groove is formed in scribe region to reduce cracks during dicing, then crack propagation is suppressed, but edge surfaces become concave causing discontinuous conductive seed layer
Solution Approach 1:
The liner and cap layers are formed in advance before the dicing process. These preliminary layers provide mechanical support to the low-k material during dicing to suppress cracks, and simultaneously create a smooth, continuous surface that enables proper deposition of the conductive seed layer, thus resolving both the crack suppression and manufacturing precision requirements
Solution Approach 2:
The solution adds dimensional complexity by introducing multiple protective layers (liner and cap) that extend the structural support into the vertical dimension. This multi-layer approach provides crack suppression during dicing while maintaining surface continuity for subsequent conductive layer deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the mechanical strength of the semiconductor device, reduces crack propagation, and ensures a continuous conductive seed layer, improving the yield and reliability of semiconductor chips by providing a stable foundation for conductive pillars.
Implementation Method 1
a low-k film of an insulating material, such as silicon oxycarbide (SiOC) and silicon carbonitride (SiCN), having a low dielectric constant (k) that exhibits weaker electric polarization between conductive layers
Implementation Method 2
a conductive seed layer may be formed as an initial step of electroplating of the conductive material
Data Source
AI summary
Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.