SDRAM Timing Drift Compensation via Periodic Write Training
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Solution Overview
Problem
Existing SDRAM systems face challenges in compensating for signal timing drift due to temperature changes, particularly at high memory speeds, where conventional training methods either impact system latency or require idle downtime, limiting their effectiveness in maintaining proper alignment of write clock and data signals.
Innovation Solution
A method and apparatus that perform periodic write signal timing training using the MPC FIFO write/read method interspersed with mission-mode SDRAM traffic, generating test result samples, and adjusting mission-mode timing settings to minimize downtime and maintain high-speed performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional training methods are used to compensate for signal timing drift, then timing alignment accuracy is improved, but system latency increases or idle downtime is required
Solution Approach 1:
The patent implements periodic write training at predetermined intervals rather than continuous training, allowing the system to maintain timing alignment accuracy while minimizing disruption to normal operations. The periodic nature of training reduces overall latency compared to continuous training methods.
Solution Approach 2:
The patent enables mission-mode SDRAM traffic to continue operating during the write training process by using separate command channels. This allows useful data operations to proceed continuously without interruption, eliminating idle downtime while still performing timing calibration.
2Reliability
If periodic write training is performed to maintain timing alignment, then timing drift compensation is improved, but system productivity decreases due to training overhead
Solution Approach 1:
The patent segments the training process into separate write training and read training phases, allowing them to be performed independently and efficiently. This segmentation reduces the total time required for complete training while maintaining timing alignment accuracy for both write and read operations.
Solution Approach 2:
The patent uses a multi-purpose command (MPC) FIFO structure that serves dual functions: normal data storage during mission-mode operations and training data storage during calibration periods. This universal structure eliminates the need for separate dedicated training memory, improving system productivity.
3Productivity
If write training is interspersed with mission-mode traffic, then system operational efficiency is improved, but training accuracy may be affected by traffic interference
Solution Approach 1:
The patent introduces a dedicated training command channel that acts as an intermediary between the controller and SDRAM for training operations. This separate channel isolates training traffic from mission-mode traffic, preventing interference while allowing both to operate simultaneously, thus maintaining both productivity and training accuracy.
Data Source
AI summary
Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.