Seal Ring ESD Paths for Bonded Semiconductor Die Packages
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Solution Overview
Problem
Electrostatic charges build up during the bonding process of semiconductor die packages, leading to potential damage of logic circuitry and reduced yield due to discharge through capacitor circuitry, which is not addressed by existing technologies.
Innovation Solution
Incorporation of an electrostatic discharge (ESD) protection circuit with discharge paths in the seal ring structure that routes electrical charges from capacitor circuitry to a power management integrated circuit (PMIC), preventing damage to logic circuitry during bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor die bonding process is performed without ESD protection, then manufacturing process is simple, but logic circuitry is damaged due to electrostatic discharge
Solution Approach 1:
The patent introduces a seal ring structure as an intermediary component between the first and second semiconductor dies. This seal ring includes discharge paths that serve as a mediator to safely route electrostatic charges away from sensitive logic circuitry, preventing direct discharge damage while maintaining the bonding process
Solution Approach 2:
The discharge paths are incorporated into the seal ring structure before the bonding process occurs. This preliminary configuration ensures that when electrostatic charges build up during bonding, they can be immediately routed through the pre-established discharge paths to the capacitor circuitry, preventing logic circuitry damage before it occurs
2Productivity
If ESD protection circuit is added to route charges away from logic circuitry, then yield increases, but device complexity and manufacturing resources increase
Solution Approach 1:
The seal ring structure serves multiple functions simultaneously: it provides mechanical sealing between dies, establishes electrical discharge paths for ESD protection, and creates a structured pathway for routing charges to capacitor circuitry. This multi-functionality increases yield without proportionally increasing device complexity
3Device complexity
If electrostatic charges are allowed to discharge through capacitor circuitry, then ESD protection is not needed, but logic circuitry is damaged and yield decreases
Solution Approach 1:
The patent converts the harmful electrostatic discharge into a beneficial controlled process by directing charges through designated discharge paths in the seal ring to capacitor circuitry. Instead of allowing random discharge that damages logic circuitry, the system harnesses the discharge phenomenon and redirects it safely, transforming a harmful factor into a controlled, beneficial process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the likelihood of damage to logic circuitry, increases yield, and minimizes resource consumption by reducing scrapping of semiconductor die packages.
Implementation Method 1
Electrostatic charges build up during the bonding process of semiconductor die packages, leading to potential damage of logic circuitry and reduced yield due to discharge through capacitor circuitry
Data Source
AI summary
Some implementations herein describe apparatuses and techniques related to a semiconductor die package including a first integrated circuit die including capacitor circuitry bonded with a second integrated circuit die including logic circuitry. The semiconductor die package may include discharge paths incorporated into a seal ring structure spanning the first integrated circuit die and the second integrated circuit die. The discharge paths may lead to a power management integrated circuit included in the second integrated circuit die. During a bonding of the first integrated circuit die and the second integrated circuit die, the discharge paths incorporated into the seal ring structure may route an electrical discharge from the capacitor circuitry of the first integrated circuit die to the power management integrated circuit.