Sealed Semiconductor Package Layout for Lower Parasitic Inductance
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Solution Overview
Problem
Conventional semiconductor devices with power semiconductor elements experience surge voltages due to parasitic inductance during switching operations, limiting the regulation of induced voltages.
Innovation Solution
Incorporating a conductive block surrounding the external connection terminals and sealing the semiconductor chip, printed circuit board, and conductive block with a sealing member to reduce parasitic inductance through eddy currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wiring structure is used in semiconductor device, then device complexity is reduced, but parasitic inductance increases causing surge voltage
Solution Approach 1:
A conductive block is introduced as an intermediary component between the external connection terminal and the semiconductor chip. This conductive block provides alternative current paths that bypass the parasitic inductance of conventional wiring, thereby reducing surge voltage while maintaining structural simplicity.
Solution Approach 2:
The invention changes the electrical parameters of the connection path by introducing a conductive block with specific conductivity and geometry. This alters the inductance and resistance characteristics of the current path, reducing parasitic inductance and associated surge voltages during switching operations.
2Reliability
If conductive block is added to reduce parasitic inductance, then voltage regulation improves, but device complexity increases
Solution Approach 1:
The conductive block serves multiple functions simultaneously: it acts as an electrical conductor to provide low-inductance current paths, as a structural support element, and as a component that can be integrated into existing packaging structures. This multi-functionality reduces the need for additional dedicated components.
Solution Approach 2:
The conductive block may be constructed from composite materials or material combinations that optimize both electrical conductivity and mechanical properties. This allows the single component to achieve both electrical performance (low inductance) and structural requirements without needing separate elements.
3Object-affected harmful factors
If sealing member is used to seal conductive block, then electromagnetic shielding improves, but manufacturing complexity increases
Solution Approach 1:
The sealing member combines multiple functions into a single component: it provides electromagnetic shielding, seals the conductive block to prevent contamination, and can serve as a mounting structure. This integration simplifies the manufacturing process by reducing the number of separate assembly steps.
Solution Approach 2:
The sealing member may be implemented as a flexible seal or thin film structure that can be easily applied during manufacturing. This flexible sealing approach simplifies assembly compared to rigid enclosures, allowing for easier integration into the device packaging process while maintaining electromagnetic shielding effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration effectively suppresses parasitic inductance and induced voltages, ensuring the semiconductor device operates within safe voltage limits by reducing magnetic fields and parasitic inductance.
Implementation Method 1
a first conductive block provided to surround an outer circumference of the first external connection terminal in an insulated state
Data Source
AI summary
A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; a printed circuit board provided over and electrically connected to the semiconductor chip; a first external connection terminal electrically connected to the conductive plate and extending upward from the conductive plate; a first conductive block provided to surround an outer circumference of the first external connection terminal in an insulated state; and a sealing member provided to seal the semiconductor chip, the printed circuit board, and the first conductive block.


