Sealing Ring Routing Layout for Narrower Semiconductor Scribe Lines
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Solution Overview
Problem
The formation of routing wiring overlapping with a scribe line increases the width of the scribe line, reducing the number of semiconductor devices obtainable from a single wafer.
Innovation Solution
The routing wiring is positioned between the outer edge of the uppermost conductor and the outer edges of underlying conductors, allowing efficient utilization of vacant areas and reducing the scribe line width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If routing wiring is formed at a position overlapping with the scribe line, then the routing wiring can be easily connected to pads for inspection, but the width of the scribe line increases, reducing the number of semiconductor devices that can be obtained from a single wafer
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by forming the routing wiring in an upper layer that overlaps with the scribe line in plan view, while the underlying conductors are positioned in lower layers. This dimensional arrangement allows the routing wiring to access inspection pads without increasing the effective scribe line width, as the overlap occurs in the vertical dimension rather than consuming horizontal space.
Solution Approach 2:
The sealing ring is divided into multiple laminated conductors at different vertical levels, with the routing wiring segregated in an upper layer. This segmentation allows different functional elements (sealing ring conductors and routing wiring) to occupy the same horizontal footprint without interfering with each other, enabling the routing wiring to overlap the scribe line while maintaining device density.
2Reliability
If routing wiring is formed overlapping with the scribe line, then connectivity is improved, but crack propagation during dicing is exacerbated
Solution Approach 1:
By positioning the routing wiring in an upper layer that overlaps the scribe line in plan view while underlying conductors are in lower layers, the patent allows the routing wiring to maintain connectivity without being cut during dicing. The vertical separation ensures that the routing wiring remains intact while the scribe line cuts through the lower layers, preventing crack propagation into the routing wiring structure.
Solution Approach 2:
The upper layer structure acts as an intermediary protective layer that shields the routing wiring from mechanical stress and crack propagation during the dicing process. This layered configuration allows the routing wiring to serve as a stress-relief layer that prevents cracks from propagating from the scribe line into the functional conductors.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a sealing ring, and at least one routing wiring. The semiconductor substrate has a peripheral region in plan view. The sealing ring is formed on the peripheral region. The sealing ring includes a plurality of conductors and a plurality of first plugs. Each of the plurality of conductors is laminated along a thickness direction of the semiconductor substrate and extends along the peripheral region in plan view. Each of the plurality of conductors has an outer edge and an inner edge in plan view. The plurality of conductors includes a first conductor located at the uppermost layer and a plurality of second conductors located below the first conductor. The outer edge of the first conductor is positioned outside any of outer edges of each of the plurality of second conductors.