Sector-Aligned Memory Layout for High-Bandwidth FPGA Data Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices face a dilemma between limited in-fabric memory capacity and slower external memory access, which affects their performance in tasks like machine learning and image recognition, as increasing in-fabric memory reduces the number of available logic elements.
Innovation Solution
Implementing sector-aligned memory, which is physically located on a separate die near the programmable logic fabric, providing higher capacity and bandwidth by dividing it into sectors that can transfer data in parallel, allowing faster data utilization and caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If in-fabric memory capacity is increased, then memory capacity is improved, but the number of available programmable logic elements is reduced
Solution Approach 1:
The patent divides the memory system into two distinct segments: traditional in-fabric memory located within the programmable logic fabric, and sector-aligned memory located in a separate memory array. This segmentation allows each memory type to serve different purposes - in-fabric memory for fast access by logic elements and sector-aligned memory for high-capacity storage - thereby increasing overall memory capacity without reducing the number of available logic elements.
Solution Approach 2:
The patent introduces a new spatial dimension by placing memory in a separate physical location (sector-aligned memory array) rather than confining all memory to the fabric. This dimensional separation allows the system to access both fast in-fabric memory and high-capacity external memory, resolving the trade-off between memory capacity and logic element availability.
2Quantity of substance
If external memory is used, then memory capacity is improved, but access speed deteriorates
Solution Approach 1:
The patent implements local quality by providing different memory types in different locations: in-fabric memory with fast access characteristics located within the fabric for speed-critical operations, and sector-aligned memory with high capacity located externally for storage-critical operations. This allows the system to optimize for both speed and capacity in appropriate contexts.
Solution Approach 2:
The patent introduces sector-aligned memory as an intermediary between the programmable logic fabric and external memory systems. This intermediary provides a buffer that can be quickly accessed by the fabric when needed, reducing the impact of slower external memory access while maintaining the benefits of high-capacity storage.
3Speed
If in-fabric memory is used, then access speed is improved, but memory capacity is reduced
Solution Approach 1:
The patent merges two different memory systems - in-fabric memory and sector-aligned memory - into a unified memory architecture. This combination allows the system to leverage the fast access speed of in-fabric memory while simultaneously utilizing the high capacity of sector-aligned memory, thereby achieving both speed and capacity improvements.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.