Sector-Aligned Memory Architecture for Parallel FPGA Data Caching

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Solution Overview

Problem

Programmable logic devices face a dilemma between limited in-fabric memory capacity and slower access times due to the space required for configuration memory, which affects their performance in tasks like machine learning and image recognition.

Innovation Solution

Implementing sector-aligned memory, which is physically located on a separate die near the programmable logic fabric, providing higher capacity and bandwidth by dividing it into sectors that can transfer data in parallel, thus enabling faster data utilization and caching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If in-fabric memory capacity is increased, then data access speed is improved, but the number of available programmable logic elements is reduced

Engineering Contradiction:

Improvedata access speedVSAvoidnumber of programmable logic elements

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent divides the memory system into two distinct segments: in-fabric memory (distributed within the programmable logic fabric) and external memory (separate from the fabric). This segmentation allows each memory type to serve different purposes - in-fabric memory provides fast access for critical data while external memory provides bulk storage, thereby improving data access speed without consuming all the die space that would otherwise be available for programmable logic elements.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary interface between the programmable logic fabric and external memory. This interface includes memory controllers and interface circuitry that manage data transfer between the fabric and external memory, enabling fast access to large amounts of data without directly consuming fabric resources. The intermediary layer abstracts the complexity of external memory access while providing high-speed data transfer capabilities.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If in-fabric memory capacity is increased, then memory capacity is improved, but die space for configuration memory is reduced

Engineering Contradiction:

Improvememory capacityVSAvoiddie space for configuration memory

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture. External memory is positioned in a separate layer or dimension above or below the programmable logic fabric, connected through vertical interconnects. This dimensional change allows the system to provide large memory capacity without consuming additional lateral die space on the fabric layer, thereby preserving space for configuration memory and programmable logic elements.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If external memory is used, then memory capacity is improved, but data access time is increased

Engineering Contradiction:

Improvememory capacityVSAvoiddata access time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements a caching mechanism where frequently accessed data is pre-loaded into in-fabric memory from external memory. The system anticipates future data access patterns and prepares data in advance in the faster in-fabric memory, thereby reducing the effective access time for commonly used data while maintaining the large capacity of external memory for bulk storage.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent employs pipelined data transfer mechanisms that continuously move data between external memory and in-fabric memory in the background while processing operations occur in the foreground. This continuous data prefetching and transfer ensures that data is ready when needed, maintaining high utilization of the programmable logic fabric without being bottlenecked by memory access delays.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11257526B2Sector-aligned memory accessible to programmable logic fabric of programmable logic device

Publication Date: 2022.02.22 ALTERA CORP

AI summary

An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.