Secure-IP Interposer Logic for Chiplet Supply Chain Integrity
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Solution Overview
Problem
The lack of control over the supply chain in the assembly of chips and chiplets leads to vulnerabilities in intellectual property security, enabling the production of counterfeit products that can be used for unintended applications, posing a national security risk.
Innovation Solution
Integrating chip logic into interposer substrates, utilizing cipher-based verification, PKI-based certificate authentication, and secure boot mechanisms to authenticate and verify the trustworthiness of interposer components, ensuring only authorized components are used in system-in-packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip logic is integrated into interposer substrates with verification mechanisms, then intellectual property security is improved, but device complexity increases
Solution Approach 1:
The interposer substrate acts as an intermediary component between the chip and the external environment, embedding verification logic and data storage devices within it. This intermediary structure enables security functions to be performed at the interposer level rather than requiring complex modifications to the chip itself or the external packaging, thus improving IP security while managing device complexity through functional distribution.
Solution Approach 2:
The patent merges multiple functions into the interposer substrate: physical support, electrical interconnection, data storage, and security verification. By combining these functions into a single integrated component, the system achieves improved IP security without proportionally increasing overall device complexity, as the interposer naturally serves as the central interconnection element in heterogeneous integration architectures.
2Reliability
If verification logic and data storage devices are embedded in interposers, then counterfeit product prevention is improved, but manufacturing complexity increases
Solution Approach 1:
The verification system is segmented into separate functional modules: verification logic embedded in the interposer, data storage devices positioned in the interposer, and cryptographic operations distributed between chip and interposer. This segmentation allows each component to be manufactured and tested independently using existing processes, reducing manufacturing complexity while achieving robust counterfeit prevention through the combined verification system.
Solution Approach 2:
The verification logic and data storage devices are embedded in the interposer during its manufacturing process, before the chip is packaged with the interposer. This preliminary action allows security features to be integrated into the interposer structure itself, simplifying subsequent assembly processes and enabling verification capabilities to be established before final system integration, thereby reducing overall manufacturing complexity.
3Reliability
If cipher-based verification and PKI authentication are implemented, then supply chain integrity is improved, but computational overhead increases
Solution Approach 1:
Different verification mechanisms are applied locally based on security requirements: cipher-based verification logic is embedded in the interposer for continuous verification, while PKI certificate authentication is used for initial identity verification. This local differentiation allows the system to use computationally intensive PKI only when necessary for authentication, while relying on lighter cipher-based verification for ongoing operations, thus improving supply chain integrity while managing computational energy consumption.
Data Source
AI summary
To protect chip intellectual property disclosed to supply chain foundries and assembly sites, an aspect stores chip logic for a chip function in an interposer. A method provides an interposer substrate; provides a data storage device in the interposer substrate and comprising chip logic to perform a chip function; and provides a via or connection in the interposer substrate between a bond pad and the data storage device. A system has an interposer comprising: an interposer substrate, a data storage device in the interposer substrate and comprising chip logic to perform a chip function; and a chip in signal communication with the interposer, wherein the chip does not comprise the chip logic, wherein the chip is to perform a function via the chip logic of the interposer.