Secure Scan Circuit Using Delayed Key Capture
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Solution Overview
Problem
Existing Design For Test (DFT) techniques in semiconductor integrated circuits and system on chips (SOCs) provide security vulnerabilities through scan chain access, which can be exploited for malicious activities, and existing security enhancements, such as using serialized flip-flops, increase complexity without significantly improving security.
Innovation Solution
A semiconductor integrated circuit design that includes a secure key circuit generating delayed input signals, a key comparator for verification, a scan output remapper for obfuscation, and a secure scan controller to control these components, enhancing security without additional flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serialized flip-flops are used to capture test scan input signal, then security is improved, but device complexity increases
Solution Approach 1:
The test scan input signal is divided into multiple segments (first test scan input signal, second test scan input signal, third test scan input signal) that are captured at different timing relative to the clock signal. This segmentation allows the generation of multiple key signals (first key signal, second key signal, third key signal) that are combined to form the authentication key, thereby improving security without requiring a single complex preset key.
Solution Approach 2:
The patent performs preliminary actions by capturing the test scan input signal at multiple different timing points before the final authentication is performed. The delay elements introduce predetermined delays to create temporally separated signal captures, allowing the system to pre-generate multiple key components that are later combined for authentication, thus enhancing security before the actual access control decision.
2Reliability
If multiple flip-flops are connected in series to increase security, then security is improved, but chip size increases
Solution Approach 1:
The patent merges multiple key signals (first key signal, second key signal, third key signal) generated from the same test scan input signal but captured at different timings into a single authentication key. This combining approach allows the system to achieve enhanced security through temporal diversity rather than spatial multiplication of flip-flops, thereby reducing the overall chip area required compared to using multiple separate flip-flop chains.
Solution Approach 2:
Instead of increasing security by adding more flip-flops in the spatial dimension (which increases chip area), the patent introduces temporal dimension by capturing the same signal at different time points using delay elements. This dimensional shift from spatial to temporal diversity allows security enhancement without proportionally increasing the chip area.
3Ease of operation
If scan chain access is provided for testing, then testing capability is improved, but security vulnerabilities increase
Solution Approach 1:
The patent introduces an intermediary authentication mechanism between the test scan input signal and the internal circuit access. The generated authentication key acts as a mediator that must be verified before allowing scan chain access. This intermediary layer maintains the testing capability by allowing legitimate test access while preventing unauthorized access, thus addressing the security vulnerability without compromising testing functionality.
Data Source
AI summary
A semiconductor integrated circuit to receive a test scan input, a test clock, and a test mode signal and output a secure scan output signal, the integrated circuit including: a secure key circuit to generate delay input signals, which are differently delayed from the test scan input, and to generate an input key signal by capturing the delay input signals in response to the test clock; a key comparator to generate a verification result indicating whether an input key of the input key signal is identical with a preset reference key; a chip to generate a scan output signal based on the test scan input; a scan output remapper to obfuscate the scan output signal according to the verification result and to output the obfuscated scan output signal as the secure scan output signal; and a secure scan controller to control the secure key circuit, key comparator, chip, and remapper.