Security Chip Clock Gating for Template Attack Resistance
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Solution Overview
Problem
Existing security chips are vulnerable to template attacks, which involve creating a template from a sample chip's current profile to deduce its key value, and evolving methods to prevent these attacks through random current generation are ineffective.
Innovation Solution
A security chip with a clock gating type generator that generates a unique clock gating type based on chip-specific parameters, distributing different current consumption patterns among flip-flop groups through first and second gating modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simple random currents are generated inside the chip during operation, then template attack prevention is attempted, but the prevention is ineffective against evolving template attack techniques
Solution Approach 1:
The patent implements dynamic clock gating control where the gating signal is generated based on real-time operation states and chip-specific parameters. The clock gating type generator dynamically selects different gating patterns (first gating mode or second gating mode) depending on the operational context, making the current consumption profile adaptive and unpredictable. This dynamic approach prevents template attacks by ensuring that identical operations do not produce identical current signatures, thereby resolving the contradiction between reliability and adaptability.
Solution Approach 2:
The patent changes the parameter of clock signal gating control based on chip-specific parameters and operation states. By varying the clock gating type (first or second gating mode) according to different operational conditions and unique chip characteristics, the system creates diverse current consumption patterns. This parameter variation ensures that even identical operations produce different current profiles across different chips and time periods, effectively preventing template attacks while maintaining security functionality.
2Reliability
If clock gating modes with different current consumption patterns are implemented, then distinct current profiles are achieved, but device complexity increases
Solution Approach 1:
The patent segments the clock distribution system into multiple independent clock gating control circuits, each associated with specific flip-flop groups. The clock gating type generator divides the chip into different operational zones that can be controlled independently. This segmentation allows the system to achieve complex current consumption patterns through coordinated control of multiple simple gating units, rather than requiring a single complex gating mechanism, thereby resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent implements a universal clock gating control architecture where the clock gating type generator and control circuits serve multiple functions: they manage clock distribution, generate security patterns, and create diverse current profiles. The same gating infrastructure is used across different chip instances and operational modes, providing multi-functionality that achieves template attack prevention without proportionally increasing device complexity. This universal approach allows the system to handle various security requirements using a unified control mechanism.
Data Source
AI summary
A security chip including: a clock gating type generator configured to generate a clock gating type based on chip-specific parameters; and a main operation unit including a plurality of flip-flop groups, wherein each of the plurality of flip-flop groups is configured to receive a clock signal at a clock input terminal in a first gating mode or a second gating mode, wherein the first gating mode results in a different current consumption pattern compared to the second gating mode.