Seedless Copper Interconnects for MEMS TWIDS Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current through-wafer interconnect technologies face challenges in reducing via size, achieving low resistance, and compatibility with standard semiconductor processing, particularly for three-dimensional packaging of MEMS devices, with complex fabrication processes leading to high resistance and void formation issues.
Innovation Solution
The development of a sonic-assisted seedless copper electroplating process for forming high-aspect ratio through-wafer interconnects, which eliminates the need for additional conductive layer deposition and sacrificial wafers, allowing for efficient co-fabrication of released silicon-on-insulator sensors and interconnects on the wafer level, utilizing the front and back sides of the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional electroplating processes are used to form through-wafer interconnects, then conductive layers can be deposited, but the process becomes complex requiring multiple layers (insulating/seed/conductive) and sacrificial wafers
Solution Approach 1:
The patent removes the insulating layer and sacrificial wafer from the conventional electroplating process. By using direct copper electroplating on the silicon surface, it extracts the unnecessary intermediate layers while maintaining the through-wafer interconnect function, thereby simplifying the fabrication process and reducing device complexity
Solution Approach 2:
The silicon substrate serves multiple functions: it acts as both the structural support and the seed layer for copper electroplating. This multi-functionality eliminates the need for separate seed layers and insulating layers, reducing the number of fabrication steps while maintaining process effectiveness
2Manufacturing precision
If seed layer deposition is used in electroplating, then copper can be deposited, but uneven seed layer deposition and void formation occur
Solution Approach 1:
The patent uses the silicon substrate itself as a temporary seed layer that is consumed during the electroplating process. The silicon surface provides the necessary nucleation sites for copper deposition, and any residual silicon is removed in subsequent processing, eliminating void formation issues associated with persistent seed layers
Solution Approach 2:
The patent modifies the electroplating parameters (electrolyte composition, voltage, current density) to enable direct copper deposition on silicon without requiring a separate seed layer. These parameter changes ensure uniform copper deposition and prevent void formation by optimizing the nucleation and growth conditions
3Reliability
If through-wafer holes are etched for molten metal penetration, then low resistance interconnects can be formed, but the process requires two openings and is incompatible with SOI sensor co-fabrication
Solution Approach 1:
The patent performs preliminary patterning of the silicon substrate to define the interconnect locations before electroplating. This preliminary action creates precise copper deposits that form low-resistance paths without requiring through-wafer holes, enabling compatibility with SOI sensor co-fabrication while maintaining low electrical resistance
Solution Approach 2:
The patent transitions from three-dimensional through-wafer holes to two-dimensional surface patterning followed by controlled copper deposition. This dimensional change allows low-resistance interconnects to be formed without penetrating through the wafer, thereby enabling co-fabrication with SOI sensors on the same substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves resistance values as low as 160 milli-ohms and minimizes parasitic capacitance, resulting in improved signal quality with amplitude and phase distortion estimates of 1.15 dB and 5.96 degrees, respectively, suitable for MEMS applications.
Implementation Method 1
filling the blind via with metal by seedless metal electroplating
Implementation Method 2
A sonic-assisted seedless copper electroplating process is developed for forming high-aspect ratio through-wafer interconnects
Data Source
AI summary
A high-aspect ratio low resistance through-wafer interconnect for double-sided (TWIDS) fabrication of microelectromechanical systems (MEMS) serves as an interconnection method and structure for co-integration of MEMS and integrated circuits or other microcomponent utilizing both sides of the wafer. TWIDS applied to a three dimensional folded TIMU (timing inertial measurement unit) provides a path for electrical signals from sensors on the front side of the SOI wafer to electronic components on the back side of the wafer, while enabling folding of an array of sensors in a three dimensional shape.