Segmented Alignment Marks for Semiconductor Stress Relief
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Solution Overview
Problem
In semiconductor manufacturing, the dicing process often results in peeling phenomena and electrical failures due to uneven stress distribution and large local stress in long metal alignment marks, which can lead to short circuits and poor reliability of semiconductor structures.
Innovation Solution
A semiconductor structure and fabrication method featuring a passivation layer with multiple sub-alignment marks arranged along the scribe line region, spaced apart to reduce stress and prevent peeling, with each sub-alignment mark having a specific rectangle shape and dimensions to ensure uniform stress distribution and minimize the risk of electrical failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a long metal alignment mark is formed in the scribe line region, then alignment precision is improved, but stress distribution becomes uneven and local stress increases causing peeling during dicing
Solution Approach 1:
The alignment mark structure is segmented into multiple parts: the scribe line region is divided into first and second regions, and the metal alignment mark is divided into a first metal alignment mark and a second metal alignment mark. This segmentation reduces the length of each individual metal alignment mark, improving stress distribution uniformity while maintaining overall alignment precision through the combined structure.
2Measurement precision
If a long metal alignment mark is formed, then alignment functionality is improved, but peeling phenomenon occurs during dicing process
Solution Approach 1:
The metal alignment mark is segmented into multiple shorter marks (first and second metal alignment marks) positioned in different regions. This reduces the length of each mark, preventing peeling during dicing while maintaining alignment functionality through the distributed arrangement of multiple marks.
Solution Approach 2:
Different regions of the scribe line are assigned different structures: the first region contains a first metal alignment mark, while the second region contains a second metal alignment mark. This local differentiation optimizes each region's properties to prevent peeling while maintaining overall alignment functionality.
3Measurement precision
If metal alignment mark length is increased, then alignment precision is improved, but brushed metal contact with seal ring and circuit increases causing short circuit risk
Solution Approach 1:
The alignment mark is segmented into multiple shorter marks positioned in separate regions. This reduces the likelihood that brushed metal from a single long mark will contact the seal ring and circuit, thereby reducing short circuit risk while maintaining alignment precision through the combined positioning information from multiple marks.
Data Source
AI summary
A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, and the substrate includes a scribe line region. The semiconductor structure also includes a device layer over the substrate. The device layer includes multiple devices, an interconnection structure electrically connected to the devices, and a dielectric layer surrounding the devices and the interconnection structure. Further, the device layer includes a passivation layer over the device layer, and an alignment mark in the passivation layer over the scribe line region. The alignment mark includes two or more sub-alignment marks, the two or more sub-alignment marks are arranged along an extension direction of the scribe line region, and adjacent sub-alignment marks of the two or more sub-alignment marks are spaced apart from each other.