Segmented Back Gate Vertical Transistor for CMOS Scaling
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Solution Overview
Problem
In CMOS technology, scaling down MOSFETs to smaller dimensions leads to challenges in controlling threshold voltage (Vt) due to dopant fluctuations, and FETs with back bias suffer from undesired parasitic capacitance caused by the large overlap of the back gate with the transistor structure.
Innovation Solution
The method involves forming vertical transistors with a back gate placed only on the source side, using a thick insulator layer between the back gate and the bottom spacer, and a thinner back gate stack that extends from the insulator to the top spacer, reducing parasitic capacitance and allowing for modulation of the barrier height at the source-channel junction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a back gate is added to control threshold voltage, then Vt control is improved, but parasitic capacitance increases due to large overlap of the back gate with the transistor structure
Solution Approach 1:
The back gate is segmented into two distinct parts: a first back gate electrode positioned over the source region and a second back gate electrode positioned over the drain region, with the channel region between them. This segmentation reduces the continuous overlap area between the back gate and the channel, thereby reducing parasitic capacitance while maintaining threshold voltage control capability through independent biasing of each segment.
Solution Approach 2:
Different regions of the back gate are assigned different functions: the first back gate electrode primarily controls the source-side potential and threshold voltage, while the second back gate electrode controls the drain-side potential. This local differentiation allows for optimized electric field distribution and reduced parasitic effects in each region while maintaining overall Vt control.
2Productivity
If MOSFETs are scaled to smaller dimensions, then device density is improved, but threshold voltage control deteriorates due to dopant fluctuations
Solution Approach 1:
The invention transitions from planar gate control to three-dimensional vertical fin structures with multiple gate electrodes (front gate and segmented back gates) acting on the channel from different spatial dimensions. This multi-dimensional gate control provides enhanced electrostatic control over the channel, compensating for dopant fluctuations and enabling precise threshold voltage control in scaled devices.
Solution Approach 2:
The device employs composite material structures including high-k dielectric materials for gate insulators and selectively doped semiconductor regions. These composite structures enable fine-tuned electrical characteristics and improved control over threshold voltage in scaled devices by combining materials with complementary properties.
Data Source
AI summary
A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the back gate are symmetric and arranged on opposing sides of a channel between the front gate and the back gate. The channel extends from a drain to a source. The method includes disposing a mask to cover the front gate and removing the back gate. The method further includes replacing the back gate with a layer of insulator and another back gate stack. The another back gate stack only covers a junction between the channel and the source, and remaining portions of the back gate are the layer of insulator.