Segmented Bit Line for Flash Memory Reducing Parasitic Effects
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Solution Overview
Problem
As NAND flash design rule scaling down and increasing memory capacity lead to narrower and longer bit lines with reduced spacing, resulting in increased parasitic capacitance and resistance, which decreases data throughput.
Innovation Solution
The bit lines are segmented into multiple segments, allowing selective grounding of bias transistors at each segment to reduce parasitic capacitance and resistance, thereby improving data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit line width is scaled down to increase memory capacity, then memory density is improved, but parasitic capacitance and resistance increase
Solution Approach 1:
The bit line is divided into multiple segments with each segment having its own select transistor and bias transistor. This segmentation allows the long bit line to be broken into shorter sections, reducing the overall parasitic capacitance and resistance. Each segment can be independently controlled and grounded when not in use, further minimizing parasitic effects on the entire bit line structure.
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple bit line segments along the bit line direction. This dimensional approach allows the bit line to be organized in segments that can be independently managed, transforming the single long bit line into a multi-segment structure that reduces parasitic effects while maintaining memory capacity.
2Quantity of substance
If bit line length is increased to accommodate more memory cells, then memory capacity is improved, but data throughput decreases
Solution Approach 1:
By segmenting the long bit line into multiple shorter sections, each segment has reduced RC time delay compared to a single long bit line. This allows faster signal propagation and switching across each segment, thereby improving data throughput while still accommodating the required memory capacity through the extended segmented structure.
Solution Approach 2:
The segmented bit line structure enables dynamic control where each segment can be independently activated or grounded based on operational needs. This dynamic segmentation allows the system to optimize performance by activating only necessary segments during read/write operations, reducing the effective capacitance and resistance during active operations and improving data throughput.
3Quantity of substance
If spacing between bit lines is reduced to increase density, then memory capacity is improved, but parasitic capacitance increases
Solution Approach 1:
Segmenting the bit line reduces the total capacitance that any single segment must drive, even when bit lines are closely spaced. Each segment presents a smaller capacitive load to its select transistor, allowing for faster switching and reduced signal interference between adjacent closely-spaced bit lines, thereby maintaining high density while managing parasitic capacitance.
Solution Approach 2:
The bias transistors are positioned to ground each bit line segment before read operations occur. This preliminary grounding action discharges accumulated charge and reduces the effective parasitic capacitance on each segment prior to data access, minimizing capacitive coupling effects between closely-spaced bit lines and maintaining signal integrity despite reduced spacing.
Data Source
AI summary
A memory device including segmented bit lines with memory cells coupled to a data cache is provided. A segmented bit line includes a bias transistor to selectively connect the bit line to a source line. Further, a physical implementation showing a segmentation pattern of the memory device is also provided.