Segmented Bit Line 3D Memory for Reduced Power and Write Disturb

The patent segments the memory array into multiple blocks, each with its own dedicated bit lines and word lines. This segmentation isolates the electrical characteristics of each block, preventing the cumulative capacitance and resistance effects that occur in large fan-out arrays. Each block operates independently with controlled line lengths, maintaining low power dissipation while achieving high overall density through vertical stacking of multiple segmented blocks.

The memory array is divided into multiple isolated blocks, each with controlled fan-out to adjacent blocks only. This segmentation prevents the cumulative write-disturb effects that occur in large continuous arrays, as cells in one block do not interact with cells in other blocks during write operations. The segmented structure maintains data integrity by limiting the scope of electrical interactions to small, controlled groups of cells.

The patent transitions from a two-dimensional layout with long array lines to a three-dimensional structure with multiple stacked memory blocks. Each block has short local bit lines and word lines, and vertical connections are minimized by having each block connect to only two global lines (one bit line and one word line). This dimensional change allows short line lengths within blocks while achieving high density through vertical stacking, resolving the contradiction between chip area and array line length.

The patent merges multiple segmented bit lines and word lines into global bit lines and global word lines that span multiple blocks. This merging reduces the total number of independent lines needed, as each global line serves multiple blocks. The segment switch devices are integrated into the memory cell structure itself, utilizing the same fabrication processes and device types, which minimizes the increase in device complexity while achieving reduced power consumption through the segmented architecture.