Segmented Bit Line Architecture for Memory Read Stability

Solution Overview

Problem

The close spacing of complementary bit lines in semiconductor memory devices leads to significant capacitance, resulting in slow read and write access times and signal noise degradation due to capacitive coupling.

Innovation Solution

The implementation of switches that divide complementary bit line structures into upper and lower local bit lines, reducing capacitance by decoupling them during write operations and coupling them during read operations, thereby improving access times and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If complementary bit lines are closely spaced to reduce area, then area is reduced, but capacitance increases leading to slow access times and signal noise degradation

Engineering Contradiction:

Improvememory device areaVSAvoidread and write access times

Core Design Contradiction:

Area of stationary objectVSSpeed

Solution Approach 1:

The bit line structure is segmented into multiple sections along the column, with isolation structures placed between segments. This segmentation reduces the capacitive coupling between adjacent bit lines while maintaining close spacing within each segment, thereby improving access times without significantly increasing area.

Inventive Principle:

Principle #1Segmentation

2Area of stationary object

If complementary bit lines are closely spaced to reduce area, then area is reduced, but signal noise margins deteriorate due to capacitive coupling

Engineering Contradiction:

Improvememory device areaVSAvoidsignal noise margins

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The bit line structure is segmented into multiple sections along the column, with isolation structures placed between segments. This segmentation reduces the capacitive coupling between adjacent bit lines while maintaining close spacing within each segment, thereby improving access times without significantly increasing area.

Inventive Principle:

Principle #1Segmentation

3Speed

If bit line length is reduced to improve access times, then access times are improved, but the number of bit line structures increases leading to larger area

Engineering Contradiction:

Improveaccess timesVSAvoidmemory device area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The bit line structure is segmented into multiple sections along the column, with isolation structures placed between segments. This segmentation reduces the capacitive coupling between adjacent bit lines while maintaining close spacing within each segment, thereby improving access times without significantly increasing area.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10854282B2Memory read stability enhancement with short segmented bit line architecture

Publication Date: 2020.12.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.